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Thread: Peculiar Problem with Quartus 17.0 lite

  1. #1
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    Default Peculiar Problem with Quartus 17.0 lite

    I am facing a peculiar problem while synthesizing with Quartus 17.0 lite for MAX 10 FPGA.

    I was just trying to interface FPGA to LTC2400 ADC in free running mode. The program basically receives serial data and
    extracts 14 bits from the parallel data stream. Everything works fine with the following statement
    ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd1;

    When I change the above code to

    ADC_DAT <= {2'b0,ADC_TEMP[27:14]}-16'd100;

    The data that I see through In system sources and probes editor is very random. Data continuously varies. When I do change back to my orginal
    statement, things works fine. Any clues?

    P.S: I will not be able to share the source code.

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    Default Re: Peculiar Problem with Quartus 17.0 lite

    P.S: I will not be able to share the source code.
    But you should be able to ask meaningful questions, though. At least if you expect answers.
    It's just mysterious how the posted line of code should be related to processing the 24 bit SPI output data of LTC2400. Why copying only 14 bits, why subtracting a certain value?

    P.S.: I notice that LTC2400 has a rather unusual data format, needs some conversion to get to regular SIGNED numbers.

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    Default Re: Peculiar Problem with Quartus 17.0 lite

    Ok Let me explain in detail. Yes LTC2400 outputs 0-16777216 corresponding to 0-2.048V input ( 2.048 is used as Vref). I require only 1mV resolution for my application. So when I supply input of 1.25V, I get 10240000 counts. When right shifted by 10 bits and suffixing 2'b0, I get 10,000 counts which I display as 10.000 volts. This is the rationale for bits extraction. By the way this code runs like a horse in modelsim. But when synthesized and downloaded into the device, the execution goes crazy when subtracting 100.

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    Default Re: Peculiar Problem with Quartus 17.0 lite

    Did you consider that the subtraction might result in an overflow?

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    Default Re: Peculiar Problem with Quartus 17.0 lite

    Yes but I have an input which is providing offset eqvt of 100 counts, so subtracting normalizes the calculation. It is taken care. Even if it overflows, the counts cannot (should not) go random. This is my concern. Am I unluckily dealing with counterfeit IC?

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    Default Re: Peculiar Problem with Quartus 17.0 lite

    Hi one thing that was overlooked by me is the critical warning which says that I have not provided any sdc constraints file. Could that be the cause of the random variations. This is because now I am experiencing a opposite result with reference to post1.

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    Default Re: Peculiar Problem with Quartus 17.0 lite

    Hi one thing that was overlooked by me is the critical warning which says that I have not provided any sdc constraints file. Could that be the cause of the random variations. This is because now I am experiencing a opposite result with reference to post1.

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