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Thread: Arria 10 TSE with GXB

  1. #1
    Join Date
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    Default Arria 10 TSE with GXB

    Dear Sir,

    I am working on a design on the DE5A-NET-DDR4. But it is not for 10G or 40G Ethernet.
    It is a Gigabit Ethernet design. It is from our old project. It was working well on the
    Arria 5 starter kit. It uses a TSE with LVDS design for the PCS and PMA. I am not
    modify it onto the DE5 board, by modifying the PMA into GXB. In addition, the GXB needs
    two additional clocks, tx_serial_clk and rx_cdr_refclk. I have used an fPLL to generate
    a mcgb_serial_clk for the tx_serial_clk and a 125Mhz from input pin (it is from a clock
    synthesizer si5340). The compilation is ok now. The PCS configuration is follow the
    TSE manual to set as below.

    0x13 = 0x13
    0x12 = 0x12d0
    0x00 = 0x5140
    0x14 = 0x0000
    0x00 = 0xd140

    The attached jpg file is the verilog code for the tse connection check. I don't know why the
    pcs loopback is not working.


    Regards,


    Peter Chang


    Attached Images Attached Images

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