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Thread: Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

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    Default Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

    Hi there

    I am have a severe and persistent problem with an attempt to simulate a MAX10 Qsys (platform designer) system in Modelsim. Everytime I try to run an RTL simulation from the synthesized Qsys block, I get two errors:

    # Loading basic_spi_to_flash.altera_dual_boot# ** Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed. The design unit was not found.
    # Time: 0 ps Iteration: 0 Instance: /testbench_spi/dut/dual_boot_0 File: e:/projects/trunk/max10/db/ip/basic_spi_to_flash/submodules/altera_dual_boot.v Line: 41
    # Searched libraries:
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/lpm
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/sgate
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_mf
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_lnsim
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/fiftyfivenm
    # E:/Projects/trunk/MAX10/simulation/modelsim/rtl_work
    # E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
    # E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
    # Loading basic_spi_to_flash.altera_onchip_flash
    # Loading basic_spi_to_flash.altera_onchip_flash_avmm_data_c ontroller
    # Loading basic_spi_to_flash.altera_onchip_flash_address_ran ge_check
    # Loading basic_spi_to_flash.altera_onchip_flash_convert_add ress
    # ** Error: (vsim-3033) Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
    # Time: 0 ps Iteration: 0 Instance: /testbench_spi/dut/onchip_flash_0 File: e:/projects/trunk/max10/db/ip/basic_spi_to_flash/submodules/altera_onchip_flash.v Line: 305
    # Searched libraries:
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/lpm
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/sgate
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_mf
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/altera_lnsim
    # E:/Projects/trunk/MAX10/simulation/modelsim/vhdl_libs/fiftyfivenm
    # E:/Projects/trunk/MAX10/simulation/modelsim/rtl_work
    # E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
    # E:/Projects/trunk/MAX10/simulation/modelsim/basic_spi_to_flash
    This is from a Qsys project containing a Clock Source, On--chip Flash (with dual boot setup), SPI to Avalon Master Bridge and 4 Pipeline Bridges. It is not a very complex system.

    I have tried to manually locate the missing libraries, but including them in the .do file simply creates a different error. For some reason, Quartus is simply not generating the files that it needs to for Modelsim's use. Loading of the other libraries in the project seems to be succesful and Modelsim does not complain.

    Note that I have tried this using Quartus 13.1, 16.0 and 17.1. I have attempted the simulations with Modelsim 10.2 and 10.7a (the most recent version). I have also tried this in Questa Prime. For these reasons I don't think this is a version issue.

    Please help, I am desperate. Thank you in advance.
    Last edited by stu84; May 11th, 2018 at 01:25 AM.

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    Default Re: Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

    I'm presuming you have generated the system in Platform Designer or performed at least synthesis to have the system design files generated.

    Also, you mention ModelSim. Are you using ModelSim-Intel FPGA edition or stand-alone ModelSim (SE or PE)? If you are using stand-alone ModelSim, you have to set up the IP simulation models to get compiled in the tool. The Intel edition has all this pre-compiled.

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    Default Re: Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

    Quote Originally Posted by sstrell View Post
    I'm presuming you have generated the system in Platform Designer or performed at least synthesis to have the system design files generated.

    Also, you mention ModelSim. Are you using ModelSim-Intel FPGA edition or stand-alone ModelSim (SE or PE)? If you are using stand-alone ModelSim, you have to set up the IP simulation models to get compiled in the tool. The Intel edition has all this pre-compiled.
    Hello and thank you for the reply.

    I have generated the VHDL using platform designer as well as synthesized the complete design with Quartus. I have also generated the simulation libraries. I am aware of the pre-compiled libraries in Modellsim-Intel FPGA edition, but I do not believe this to be an issue related to those as I have attempted this simulation using ModelSim-Intel FPGA edition, ModelSim PE and Questa Prime. All three simulation packages give the same error.

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    Default Re: Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

    I have some extra information on this issue:

    I tried removing the on-chip flash block and the dual-boot block from the Qsys project, regenerated and resynthesized. Now the simulation works perfectly. This leads me to believe that there is a problem with the way that Quartus is generating the simulation models for the on-chip flash and dual-boot blocks. If anyone else has experienced this, I would love to hear about it along with any possible solutions you may have found.

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    Default Re: Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

    Or it could be that the simulation models were not compiled correctly in the tool.

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    Default Re: Error: (vsim-3033) Instantiation of 'alt_dual_boot_avmm' failed.

    Quote Originally Posted by sstrell View Post
    Or it could be that the simulation models were not compiled correctly in the tool.
    This was my first thought, but it appears that the files that Modelsim is complaining about (alt_dual_boot_avmm and altera_onchip_flash_block) are not in the generated files for the simulation, despite the fact that they are instantiated by other files. This really seems to be an inherent Qsys/Platform Designer problem.

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