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Thread: DDR3SDRAM IP-core, number of chip selects

  1. #1
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    Default DDR3SDRAM IP-core, number of chip selects

    hello everyone.

    I am trying to create DDR3-IP core.
    I want to connect two DDR3-SDRAM SODIMMs(64bits) in parallel.

    each SODIMM has two chip selects pins.
    so the case needs four chip selects.

    I try to do so in QuartusPrime 15.1.
    but I only can select two chip selects.( see attached file )

    I think old version of QuartusII could set bigger number, because in that time I set the number directory.

    how can I set lager number? or can't I do that?
    Attached Images Attached Images

  2. #2
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    > because in that time I set the number directory.
    this was not true, in that time (QuartusII 12.1) you can choose 1,2,4,8.

    sorry.

  3. #3
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    Which device are you using? You may need to create two separate instances of the IP.

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    Default Re: DDR3SDRAM IP-core, number of chip selects

    hello sstrell
    thank you.

    I am using CycloneV (5CGXFC9...)
    if I need to create two separate instances, which means that data bus can not be shared right?
    I don't have enough pins for the second IP.

  5. #5
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    If you're using the hard IP, take a look at the ping pong Phy feature to share address and command pins.

  6. #6
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    I think ping pong PHY is not for cycloneV.
    I could find ping pong PHY for Arria10 but not others ( I mean cycloneV, ArriaV )

  7. #7
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    I'm pretty sure that if you use the hard IP (not the soft controller) in Cyclone V, you can use ping pong phy. Try adding the ip and check the parameter editor for the option.

  8. #8
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    Whoops, just looked it up: Arria V GZ and Stratix V only (for pre-Arria 10 devices).

  9. #9
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    Things are clear thank you anyway

  10. #10
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    Default Re: DDR3SDRAM IP-core, number of chip selects

    I believe Cyclone V doesn't support DDR3 write leveling, so no chance to use DDR3 SODIMM modules.

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