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Thread: Synchronization of data, control and clock inputs in QuartusII

  1. #1
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    Default Synchronization of data, control and clock inputs in QuartusII

    Hey everyone,

    i am getting a data(4 Bit), a control(1 Bit) and a clock signal from the Cyclone V pins which are driven by extern sources.
    These signals are misaligned and i want to align the control and the data signals to the extern clock signal in my FPGA design.

    Are there any Altera/QuartusII provided IP-Cores available to this task? What is the best method to align them?

    The deskew isn't static, so timing constrains are probably not the right solution.
    I am using Cyclone V and QuartusII 2017.

    Every help is very appreciated, thanks in advance.

    Best regards
    Last edited by fpga_fan55; May 14th, 2018 at 02:45 AM.

  2. #2
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    Default Re: Synchronization of data, control and clock inputs in QuartusII

    Add a PLL and choose one of the available clock compensation options.

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