I try migrat a desig from Cyclone V to Arria 10 with DDR inpu. I have 4 data line and 1 clock line with data rate 444.5 Mbit/s and clock rate 222.25 MHz. In Cyclone I used the ALTDDIO_IN megafuncton (I instantiated it without Megawithard) and Quartus 13.1.
Now I use Arria 10 GX and Quartus Prime Pro 17.1. When I sinthesize my code Quartus dont use DDIO registers and TimeQuest report a slacks. But in Cyclone V this design use a DDIO registers in pins block.
Also I try compilate the design with altlvds_rx core and with twentynm_ddio_in (it used in core Altera GPIO) but everething got same result: quartus dont use unput DDIO registers and inplement DDR input on LEs. Also I try use FastInpitRegisters assignmet and constrains from Altera GPIO manual, but I cant implement logic with Input DDIO registers.

Please help me use dedicaes input DDIO registers.