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Thread: drive the input pins during the power-up/down sequence

  1. #1
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    Default drive the input pins during the power-up/down sequence

    Hi,
    Can I set the output of the external, peripheral chips(connected to the FPGA Arria10) in the in the VCCIO-GND voltage range during the power-up/down sequence for LVDS Banks?
    Can I set the output of the external, peripheral chips(connected to the FPGA Arria10) in the in the VCCIO-GND voltage range during the power-up/down sequence for 3V Banks?

  2. #2
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    Default Re: drive the input pins during the power-up/down sequence

    Hi,

    You can find the information from the "Intel® Arria® 10 Core Fabric and General Purpose I/Os Handbook".
    Refer Table:124
    https://www.altera.com/en_US/pdfs/li...0_handbook.pdf

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

  3. #3
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    Default Re: drive the input pins during the power-up/down sequence

    the table 124 shows:
    1. 3VIO banks - Tristate.
    Is it necessary to install this mode(Tristate) on the outputs of the external, peripheral chips without pull-up or pull-down resistors?
    Is it necessary to install this mode(Tristate) on the outputs of the external, peripheral chips if the VCCIO=1.8V?
    2. LVDS I/O banks - Drive to GND or Drive to VCCIO. Why can't these contacts be drived in the VCCIO-GND voltage range?

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