Results 1 to 6 of 6

Thread: PLL Warnings appearing with Quartus Prime

  1. #1
    Join Date
    May 2018
    Posts
    3
    Rep Power
    1

    Question PLL Warnings appearing with Quartus Prime

    Hi,
    I have three PLLs in my Cyclone V design.
    Since I moved from Quartus II v15.0.2 to Quartus Prime v17.1.1 I get these outlandish warnings appearing (see attached image).
    Does any one know what it's all about ?
    The design is working fine but these warnings are a bit upsetting...
    Many thanks in advance,

    Manu
    Attached Images Attached Images

  2. #2
    Join Date
    Jun 2007
    Location
    Penang
    Posts
    176
    Rep Power
    1

    Default Re: PLL Warnings appearing with Quartus Prime

    Hi,

    Looks like the cnt_sel[4:0] does not have any drivers. Due to this, the optimization tool has removed away the logic and signals associated with these 5 counter select lines. You should check if these 5 bits are being driven by any logic. If not, then you can ignore the warnings.

  3. #3
    Join Date
    May 2018
    Posts
    3
    Rep Power
    1

    Default Re: PLL Warnings appearing with Quartus Prime

    Hi,
    Thanks for your reply... I already checked the so-called "validity" of these warnings to find out that indeed I can ignore them.
    My concern is more about the fact that the same design doesn't generate any warning with Quartus II v15.0.2.
    It's always a bit unsettling when the synthesizer informs you that it threw away some part of a design !

  4. #4
    Join Date
    Dec 2007
    Location
    Bochum Germany
    Posts
    6,343
    Rep Power
    1

    Default Re: PLL Warnings appearing with Quartus Prime

    To know if necessary PLL functionality has been discarded, you need to know what the designed functionality is. That's not obvious from the quoted warnings.

    It can be better seen in the fitter resource utilization report. How is the PLL instantiated? If it's Megawizard generated IP, did you regenrate it with the recent Quartus version?

  5. #5
    Join Date
    May 2018
    Posts
    3
    Rep Power
    1

    Default Re: PLL Warnings appearing with Quartus Prime

    Hi,
    From what I can see in the fitter resource utilization report the three PLLs seem to be implemented correctly. The IPs were re-generated (using Megawizard) when I moved from v15 to Prime v17. The IP components panel says that the IPs are Altera PLL v17.1 and up-to-date.
    In my VHDL I copy the component declaration from the .cmp file generated by Megawizard in the declaration section and then I instantiate the component in the behavioral section.
    Here again, the design works as expected ! My only concern is about these somehow destabilizing warnings saying that the synthesizer threw away parts of the design !

  6. #6
    Join Date
    Dec 2007
    Location
    Bochum Germany
    Posts
    6,343
    Rep Power
    1

    Default Re: PLL Warnings appearing with Quartus Prime

    If you didn't select later unused PLL features in MegaWizard, the warnings shouldn't happen, I think. I suspect a minor Quartus bug.

Similar Threads

  1. Why the warnings and critical warnings disappear when I open the project again ?
    By buddha1987 in forum Quartus II and EDA Tools Discussion
    Replies: 3
    Last Post: December 16th, 2014, 05:43 AM
  2. 1.5 PCML lines not appearing in IBIS file
    By stu84 in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 1
    Last Post: July 17th, 2012, 02:59 AM
  3. Warnings in Quartus
    By chasecq123 in forum General Altera Discussion
    Replies: 3
    Last Post: July 19th, 2010, 12:45 AM
  4. getting quartus warnings
    By Hava in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: November 9th, 2009, 02:20 AM

Tags for this Thread

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •