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Thread: Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

  1. #1
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    Default Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

    Hello everyone,

    I've been trying to understand the workings of the timing analyser recently. I need to implement an SDRAM Controller with Uniphy in my design.
    So I opened up an example project called "SoCKit_DDR3_Nios_Test. I noticed it is very similar to mine, it has a nios processor, onchip mem, clock, and so on.

    After compiling and constraining the I received a setup violation error. I don't know what is wrong with my constraint. I doubt I need to use set_input_delay or set_output_delay, since the sdc file doesn't even have clock groupings, which I added later on to try to repair the setup slack. The clock groupings managed to correct the negative slack on the generated clock "u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk"
    This is my sdc file.

    Code:
    create_clock -period 20 [get_ports OSC_50_B3B]
    create_clock -period 20 [get_ports OSC_50_B4A]
    create_clock -period 20 [get_ports OSC_50_B5B]
    create_clock -period 20 [get_ports OSC_50_B8A]
    derive_pll_clocks
    derive_clock_uncertainty
    set_clock_groups -asynchronous -group {OSC_50_B3B \
                                                        OSC_50_B4A \
                                                        OSC_50_B5B \
                                                        OSC_50_B8A \
                                            } \
                                            -group { 
                                                        u0|pll_qsys|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] \
                                                        u0|pll_qsys|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk \
                                            } \
                                            -group { \
                                                        u0|mem_if_ddr3_emif_fpga|DDR3_Qsys_mem_if_ddr3_emif_fpga_p0_sampling_clock \
                                            } \
                                            -group { \
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_addr_cmd_clk \
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_avl_clk \
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_dq_write_clk \
                                                        u0|mem_if_ddr3_emif_fpga|pll0|pll_write_clk \
                                            } \
                                            -group { \
                                                            u0|mem_if_ddr3_emif_fpga|pll0|pll_afi_clk \
                                            } \
                                            -group { \
                                                        DDR3_CK_n \
                                                        DDR3_CK_p \
                                                        DDR3_DQS_n[0]_OUT \
                                                        DDR3_DQS_n[1]_OUT \
                                                        DDR3_DQS_n[2]_OUT \
                                                        DDR3_DQS_n[3]_OUT \
                                                        DDR3_DQS_p[0]_IN \
                                                        DDR3_DQS_p[0]_OUT \
                                                        DDR3_DQS_p[1]_IN \
                                                        DDR3_DQS_p[1]_OUT \
                                                        DDR3_DQS_p[2]_IN \
                                                        DDR3_DQS_p[2]_OUT \
                                                        DDR3_DQS_p[3]_IN \
                                                        DDR3_DQS_p[3]_OUT \
                                            } \
    I can't really wrap my head around the behind-the-scene workings of Altera. Can someone please explain me?
    I look forward to any replies

    BTW I'm using Quartus 14.1
    Attached Images Attached Images

  2. #2
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    Default Re: Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

    I can't read your screenshot to see what paths are failing, but the IP should have generated a .sdc file for you.

  3. #3
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    Default Re: Nios DDR3 Test Example Project TimeQuest Negative Setup Slack

    Oh I'm sorry about the screenshot

    Please try this link

    https://imgur.com/a/yR9lDWM

    The sdc file from the previous post was the generated sdc file. I just added the clock groups to see if that solves the failure.


    I added the source project folder to my attachments. This is in its original form.
    I would appreciate any help.
    Attached Files Attached Files

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