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Thread: With Transceivers, High-Speed Source-Synchronous Differential I/O Interfaces - LVDS

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    Default With Transceivers, High-Speed Source-Synchronous Differential I/O Interfaces - LVDS

    Is there any limitation in the Cyclone 1o GX transceiver to create LVDS signal defined as Vocm 1.25 V , 0.3V to 0.4V differential swing with 2.5 Gbps (1.25 Ghz clock) by using the external shared clock with minimum 5 transceivers for source synchronous implementation ( 1 clock 4 data late at 2.5 Gbps data rate with 1.25 GHz )?

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    Default Re: With Transceivers, High-Speed Source-Synchronous Differential I/O Interfaces - LV

    I believe that your question about LVDS standard in transceivers has already been answered in one previous threads of your Cyclone 10 GX series.

    Instead of repeating questions, you may want to study the document details in the meantime, e.g. about the difference between AC and DC coupled links.

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