Results 1 to 3 of 3

Thread: High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

  1. #1
    Join Date
    Apr 2018
    Posts
    22
    Rep Power
    1

    Default High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Devices

    Background:
    My end goal is to implement source synchronous differential IO interface with Cyclone 10 GX devices : 4 data lanes with 1 clock line at 2.5 Gbps with 1.25 GHz.
    Cylone 10 GX devices has dedicated LVDS lines with HARD IP Serializer and Deserializer which allow LVDS at 1.434 Gbps. This is a limitation in my application. I am trying to use transceivers for 2.5 Gbps instead of LVDS IO resources.


    Question:
    I am looking for a document or a design example or a reference design for High-Speed Source-Synchronous Differential I/O Interfaces in Cylone 10 GX Devices.


    Extra Information:
    For other current GX devices, it is also fine.

    I found the following document published at 2006. I am looking for a updated version of it.

    https://www.altera.com/en_US/pdfs/li...x_sgx52013.pdf

  2. #2
    Join Date
    Nov 2017
    Posts
    532
    Rep Power
    1

    Default Re: High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Device

    Hi,

    Refer session 5.2 of the handbook.
    https://www.altera.com/content/dam/a...10gx-51003.pdf

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

  3. #3
    Join Date
    Jun 2007
    Location
    Penang
    Posts
    176
    Rep Power
    1

    Default Re: High-Speed Source-Synchronous Differential I/O Interfaces in Cyclone 10 GX Device

    Last edited by eapenabrm; June 12th, 2018 at 01:32 AM.

Similar Threads

  1. Replies: 1
    Last Post: June 9th, 2018, 12:00 AM
  2. Contraining source synchronous interfaces
    By ana in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 8
    Last Post: December 19th, 2017, 11:16 AM
  3. AUTO_DELAY_CHAINS and source synchronous DDR interfaces
    By vertreko in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: July 17th, 2012, 03:55 PM
  4. How to Constraint Source-Synchronous Double-Data Rate Interfaces
    By Rysc in forum Quartus II and EDA Tools Discussion
    Replies: 4
    Last Post: October 7th, 2009, 05:38 PM
  5. Example for constraining Source Synchronous Interfaces in TimeQuest
    By ltwoodh in forum Quartus II and EDA Tools Discussion
    Replies: 1
    Last Post: March 8th, 2007, 03:32 PM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •