Results 1 to 2 of 2

Thread: MAX7000A's JTAG instruction

  1. #1
    Join Date
    Jul 2018
    Rep Power

    Red face MAX7000A's JTAG instruction

    hello, altera workers:
    I want to use MCU's GPIO to simulate the JTAG sequrence,and program the CPLD(MAX7000a) with this method.So, I want to know where can I find the JTAG instruction for MAX7000a.
    please let me know,thanks for your help.

  2. #2
    Join Date
    Nov 2017
    Rep Power

    Default Re: MAX7000A's JTAG instruction


    Hope this may help you.
    For instruction and register access information, you can refer the BSDL file and data sheet.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,
    Anand Raj Shankar
    (This message was posted on behalf of Intel Corporation)

Similar Threads

  1. CHANGE_EDREG JTAG instruction via a JAM file
    By kb_81 in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 4
    Last Post: February 12th, 2018, 08:10 AM
  2. MAX10: JTAG Instruction Set - Understanding what USBBlaster is doing - later ISP
    By markuss in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 8
    Last Post: March 28th, 2016, 06:57 PM
  3. EDERROR_INJECT JTAG instruction to simulate a CRC error in a CYCLONE IV GX devices
    By atul.bhanushali in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: September 17th, 2014, 08:34 PM
  4. nios ii psedo-instruction and equivalent instruction
    By hanshaohua in forum General Discussion Forum
    Replies: 4
    Last Post: August 29th, 2010, 04:56 PM
  5. INIT_CONF JTAG instruction code for EPC?
    By tag818 in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 2
    Last Post: June 12th, 2007, 04:47 AM

Tags for this Thread


Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts