i have some problems with test about transceiver on Arria10 GX.

My goal is: check transceiver comunication with different speed.

I have already done a test a 5Gbps with Native PHY with indipendent Tx and RX block with Standard PCS (10bit) and Bitslip. The test was successful.

Now i want to test the comunication at 10Gbps using Enhanced PCS (64bit) and Bitslip. The parallel receved are wrong, but the bitslip shift the word by 1 bit every rising edge. The receved word is wrong, because have more '1' than i send by TX.

it seems that an internal coding is applied to the block, but every block aren't enabled.

My option are:

PCS-PMA interface 64
FPGA fabric interface 64

FIFO mode phase compensation
FIFO partially full threshold :23
FIFO partially empty threshold: 2
Enable Rx data bitslip
Eenable rx_bitslip port

FIFO mode phase compensation
FIFO partially full threshold:11
FIFO partially empty threshold:2

Any advice?