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Thread: Stratix V: 10Gb interface/transceiver noob questions

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    Default Stratix V: 10Gb interface/transceiver noob questions

    I am new to this family of the chips, and in general new to fast networking (however familiar with networking in general). I searched over the internet and scanned several documents, they have plenty of technical info, but I need to understand very basics of how to "drive" the hardware. The information I will gather will influence platform and in general manufacturer I will use.

    I reads there's some IP available (not sure if it is free of charge of paid though), but I initially target to understand how hardware works at the very low level to see how to optimize the design and write my own.

    So questions are:
    1. Looking at pictures in Stratix V GX FPGA Development Board I can not understand how many networking sockets are in the cage. Four? How many channels can I connect to it?
    2. Looking into the Stratix V Device HandbookVolume 2: Transceivers figures 1-1 and 1-2. I can not understand where QSFP module physically is, and where FPGA is.
    3. If I understood correctly, the differential wire pairs between QSFP module and FPGA carry signal of 10 Gb/s speed? Is there any Altera guide on board layout?
    4. If I am not mistaken, FPGA's manual says its max frequencly is 600 MHz. But then it will not be able to cope with 10 GB/s speed as is, and will require deseiralizer and 32-bit parallel bus (8000/32~250 MHz). But figure 1-1 shows 1-bit bus width as an input to the "FPGA fabric"!
    5. In general, please point me to the resource concisely explaining Altera 10Gb technology in general without very clever pictures and too deep implementation details - where I can learn about the technology and how to drive it from physical perspective and logical perspective.
    Last edited by eugeny_brychkov; July 11th, 2018 at 11:17 PM.

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