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Thread: PLL of Cyclone V: 'reconfig_to_pll' bus description needed

  1. #1
    Join Date
    Jun 2017
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    Question PLL of Cyclone V: 'reconfig_to_pll' bus description needed

    Hi community,

    I'm working on a Project that has to be migrated from a Cyclone III to a Cyclone V FPGA.
    My problem is the PLL reconfiguration. Normally, the reconfiguration is processed by use of the PLL reconfiguration megafunction.
    In my application, I can't use this tool. For the Cyclone III, we've created a own simple design to handle the scan chain. This was possible, because the scan chain is well documented.
    Unfortunately, the PLL reconfiguration on the Cyclone V is completly different (it uses a 64Bit reconfiguration bus), and my problem is, that I could not find any description of the bus signals nor the bus timing.

    My question is: Can anybody give me a hint, where to find this information? Or has anybody a description of the bus?


    Find attached a screenshot that illustrates my question
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  2. #2
    Join Date
    Sep 2013
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    Default Re: PLL of Cyclone V: 'reconfig_to_pll' bus description needed

    Altera/Intel don't publish the details of that bus.

    Can I ask why you don't want to use the PLL_RECONFIGURE IP - as is intended for PLL reconfiguration? You're clearly intending to do some redesign work in moving to Cyclone V from Cyclone III. Why not incorporate the PLL_RECONFIGURE IP and use the two bits of IP as intended? Controlling the PLL_RECONFIGURE IP is pretty straightforward...


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