Results 1 to 5 of 5

Thread: Definition of Clock setup slack

  1. #1
    bcao Guest

    Default Definition of Clock setup slack

    From Quartus II Handbook Version 9.0 Volume 3: Verification, Chapter 7: The Quartus II TimeQuest Timing Analyzer, page 7-11.

    "If the data path is from an input port to a internal register, the Quartus II TimeQuest Timing Analyzer uses the equations shown in
    Equation 72 to calculate the setup slack time.

    Equation 7-2

    Clock Setup Slack Time
    = Data Required Time Data Arrival Time
    Data Arrival Time
    = Launch Edge + Clock Network Delay +
    Input Maximum Delay of Pin
    + Pin-to-Register Delay

    Data Required Time
    = Latch Edge + Clock Network Delay to Destination Register μtSU"

    What is the "Input Maximum Delay of Pin"? Is it the PCB trace delay to the pin?

    It seems to me that thare are 2 registers in Equation 7-2, one is the source and the other is the destination. I think that the source and the destination should be the same. If this is the case, why is the "Clock Network Delay" included in the "Data Arrival Time" calculation?

    Many thanks.


  2. #2
    Join Date
    Mar 2007
    Posts
    2,195
    Rep Power
    1

    Default Re: Definition of Clock setup slack

    There are two registers when doing timing from an input port to an internal register(there are two registers on all calculations, really). The destination register is the one in the FPGA, but the source register is the one outside of the FPGA that drives data into that port.
    When you add a constraint "set_input_delay ..." you're automatically saying there is an external register driving in on whatever port you specify. The -clock option specified what clock drives that external register. Note that it is recommended to create a virtual clock. So, for example, if I have a clock coming into the FPGA, maybe going through a PLL, and driving my input register in the FPGA, and let's say that clock is 10ns, then I might do something like:
    create_clock -period 10.0 -name ext_clock
    set_input_delay -clock ext_clock -max #.### [get_ports datain*]
    set_input_delay -clock ext_clock -min #.### [get_ports datain*]
    Note that the created clock is not assigned to anything, making it virutal, and I use it to clock the external register.
    Now we have the classic register to register path described. Assuming the clock in the FPGA is 10ns, we have a setup relationship of 10ns and a hold relationship of 0ns.
    Hopefully that gets you started, but I find looking at the actual constraints and analyzing the TimeQuest reports a lot more productive than looking at equations, because once you figure them out, you then need to see how that is done in TimeQuest.

  3. #3
    bcao Guest

    Default Re: Definition of Clock setup slack

    Thank you very much indeed, Rysc.

    You made clear about the source and destination registers.

    When you say that "the source register is the one outside of the FPGA that drives data into that port", I suppose that the source register is a virtual register. It does NOT actually exist and is imagined as a register only for timing calculation purpose. There is no way to find this info from any Altera documentation.

    In this case, I think that Input Maximum Delay of Pin is the PCB trace delay from the source register to the pin.




    Last edited by bcao; June 28th, 2009 at 11:23 PM.

  4. #4
    Join Date
    Mar 2007
    Posts
    2,195
    Rep Power
    1

    Default Re: Definition of Clock setup slack

    Yes, it's virtual. It's generally:
    Tco of the previous device + PCB delay - (PCB clock skew)
    So if the setupr relationship was 10ns between the clocks, the Tco of the external device is 4ns, the PCB delay is 0.5ns, and the clock delay to the FPGA is 200ps longer than the delay to the upstream device, then your -max input delay is 4.3ns. That means inside the FPGA your data can be 5.7ns long. You also want to do the -min calculations.
    Note that there are other ways to do the board level clock skew. You could either shift the clock edges(not recommended) or use set_clock_latency, but I've found most people just roll it into their input/output delay constraints, and that works best.

    And don't forget you can use equations. For example, if the data is coming from an ADC, put something like:

    set adc_tco_max 4.0 ;# Found on page 4-14 of ADC datasheet
    set adc_pcb_max 0.5
    set adc_fpga_max_skew .02
    set adc_delay_max [expr $adc_tco_max + $adc_pcb_max - $adc_fpga_max_skew]
    set_input_delay -clock adc_clk_ext -max $adc_delay_max [get_ports adc_inputs*]

    I'm a huge fan of this because it documents what you've done. Otherwise someone else gets the constraints(maybe years down the line) and has no idea how they were calculated, how a board re-spin would affect them, etc., but this way it's all there.

  5. #5
    bcao Guest

    Default Re: Definition of Clock setup slack

    Rsyc, your very clear explanations are highly appreciated. Thank you very much indeed.

Similar Threads

  1. How to avoid negative slack?
    By derguteweka in forum Quartus II and EDA Tools Discussion
    Replies: 6
    Last Post: March 1st, 2016, 08:52 PM
  2. Slack:Not operational: Clock Skew>Data Delay ...
    By cowoho in forum Quartus II and EDA Tools Discussion
    Replies: 2
    Last Post: March 26th, 2009, 11:30 PM
  3. Timequest reports setup violation in clock "n/a"
    By Mickey in forum Quartus II and EDA Tools Discussion
    Replies: 4
    Last Post: February 25th, 2009, 12:44 PM
  4. Be confused with setup time slack calculation
    By David_Cai in forum Quartus II and EDA Tools Discussion
    Replies: 3
    Last Post: January 8th, 2008, 05:09 PM
  5. Clock setup and hold slack explained
    By kwalt in forum Shared Material
    Replies: 1
    Last Post: October 15th, 2007, 06:49 AM

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •