Hi,
I am wondering if anybody can tell me how to set the compile order for modelsim.
I have created a small test project in VHDL where I directly instantiate an
entity (without component declaration VHDL-93).
When I start Modelsim from Quartus via the "EDA RTL Simulation" command,Code:entity comp_inst is port ( a : in std_logic; y : out std_logic ); end entity; architecture rtl of comp_inst is begin U1: entity work.my_not(rtl) port map (a, y); end rtl;
Quartus is generating a .do script with the following compile order:
Modelsim is generating the following error message during compilation.Code:vcom -93 -work work {C:/altera/work/comp_inst/comp_inst.vhd} vcom -93 -work work {C:/altera/work/comp_inst/my_not.vhd}
If I swap the compile order of the two entities and restart the *.do script withinCode:# vcom -93 -work work {C:/altera/work/comp_inst/comp_inst.vhd} # Model Technology ModelSim ALTERA vcom 6.4a Compiler 2008.08 Oct 22 2008 # -- Loading package standard # -- Loading package std_logic_1164 # -- Compiling entity comp_inst # -- Compiling architecture rtl of comp_inst # ** Error: (vcom-11) Could not find work.my_not. # ** Error: C:/altera/work/comp_inst/comp_inst.vhd(14): (vcom-1195) Cannot find expanded name "work.my_not". # ** Error: C:/altera/work/comp_inst/comp_inst.vhd(14): Unknown expanded name. # ** Error: C:/altera/work/comp_inst/comp_inst.vhd(15): VHDL Compiler exiting # ** Error: C:/altera/90/modelsim_ase/win32aloem/vcom failed. # Error in macro ./comp_inst_run_msim_rtl_vhdl.do line 8 # C:/altera/90/modelsim_ase/win32aloem/vcom failed. # while executing # "vcom -93 -work work {C:/altera/work/comp_inst/comp_inst.vhd}"
Modelsim everything is working fine.
Anyway on the next start Quartus has overwritten the modified *.do script.
Is there any way to force quartus to generate a script with the right compile order?
Thanks!
BTW I am using Quartus 9.0 Web Edition and Modelsim Altera Starter Edition 6.4a


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