[Moneyball]

I was doing a PLL reconfiguration and changing only my M counter from 3 to 6. Every time I did it, my PLL would lose lock. Couldn't figure out why but after some digging I found the answer. Any time you change something that is part of the loop (N, M, Icp, R, C) you could lose lock. You're basically breaking the loop when you change one of those parameters, so the PLL may lose lock. If you change an output counter (C) or just change your phase shift, you won't lose lock since you're not messing with the loop. This is not very intuitive, so I thought I'd pass it along.

[scsi]

Yes.
You should assert arest to relock it.

[std_logic]

I have spent a lot of time on this. Its also worth noting you can only change the post scale counters once without losing lock, if you change them again you have to apply a reset

[cheuk]

Hello MoneyBall ,

I had similar problem before
Are you using the ALTPLL_RECONFIG mega function ?
If yes , then you have to generate a mif file for the ALTPLL
And also you have to generate a mif file for the ALTPLL_RECONFIG

I missed the mif file for ALTPLL_RECONFIG
And the reconfiguration process failed

Regards ,
Samson

[cheuk]

Hello All ,

Actually , reset is not requried for the PLL reconfiguration
If a reset is asserted , all the settings of reconfiguration will be lost

For example , in the mif file , the initial phase of the PLL is 0
After the reconfiguration , the phase is increased by one
If a reset is asserted , the Phase of PLL will return to 0 , instead of the value that user has set

I have verified it on the Silicon Device

Regards ,
Samson

[engineereeyore]

Originally Posted by cheuk

Hello All ,

Actually , reset is not requried for the PLL reconfiguration
If a reset is asserted , all the settings of reconfiguration will be lost

For example , in the mif file , the initial phase of the PLL is 0
After the reconfiguration , the phase is increased by one
If a reset is asserted , the Phase of PLL will return to 0 , instead of the value that user has set

I have verified it on the Silicon Device

Regards ,
Samson

So how did you get the PLL to reacquire a lock? I've got a design that forces me to change the N value on occasion, and I can't get it to reacquire the clock. I've tried asserting reset and areset, with neither having any effect. I've run out the timing simulation to 100us, with it losing lock around 3us. It reacquires the lock if I run a functional simulation, but not if I run a timing simulation.

BTW, I'm using Quartus 6.0SP1 and a Stratix II device.

[std_logic]

PLL Reset is not required for phase increments. It is however required for other PLL settings, M, N etc.

[engineereeyore]

Originally Posted by std_logic

PLL Reset is not required for phase increments. It is however required for other PLL settings, M, N etc.

Yeah, everything work fine for post-scale counter manipulation (not implementing phase increments). Its just the changing of the N value that's giving me grief. I know it'll kill the lock, I just can't get it to lock again afterwards. I've tried resetting it, for as long as 1,000 clock cycles. Still doesn't lock again. I've tried decreasing the input frequency, I've tried all kinds of things. I just can't get it to re-lock. But this is only on timing simulation. Functional simulation it re-locks real quickly. But it just won't on timing simulation, and I can't figure out why.

[std_logic]

Might be a fault in the model. I'll try it later this week.