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Forum: IP Discussion

A place to discuss topics related to Intellectual Property and solutions

  1. Sticky Thread Sticky: IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

    Started by GuruDog, September 24th, 2009 07:53 PM
    2 Pages
    1 2
    using tse ip core
    • Replies: 16
    • Views: 93,222
    June 9th, 2015, 08:50 AM Go to last post
  1. Post Arria 10 DDR3 with Bank 3G and 3H

    Started by jtanaka, November 10th, 2017 12:48 AM
    arria 10, ddr3
    • Replies: 4
    • Views: 317
    November 14th, 2017, 07:38 PM Go to last post
  2. Is Random Number Generator available for Max 10 FPGAs?

    Started by Ozu, May 24th, 2016 01:56 AM
    max 10, rng ip
    • Replies: 3
    • Views: 1,101
    November 14th, 2017, 05:17 PM Go to last post
  3. Question Using Altera PCI AV-MM DMA IP with custom MSI interrupts

    Started by tanjomar, February 8th, 2016 09:53 AM
    pci-e dma msi interrupt
    • Replies: 2
    • Views: 1,237
    November 14th, 2017, 08:50 AM Go to last post
  4. Cyclone V Hard Memory Controller MPFE bandwidth

    Started by simonkbrown, November 14th, 2017 07:55 AM
    cyclone, ddr, hmc, mpfe
    • Replies: 0
    • Views: 77
    November 14th, 2017, 07:55 AM Go to last post
    • Replies: 0
    • Views: 80
    November 14th, 2017, 12:19 AM Go to last post
  5. Question Qsys - Generic QUAD SPI controller II support flash device

    Started by hide-u, August 30th, 2017 12:54 AM
    qspi flash, quad spi controller ii
    • Replies: 1
    • Views: 587
    November 13th, 2017, 12:15 AM Go to last post
  6. Burst size and burst length Avalon MM bridge

    Started by vittal92, March 10th, 2017 03:23 PM
    avalon, burstength, ips
    • Replies: 1
    • Views: 1,321
    November 12th, 2017, 10:03 PM Go to last post
  7. altera_dma driver for PCIe

    Started by deusdetematos, May 4th, 2017 06:01 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 1,507
    November 12th, 2017, 02:34 AM Go to last post
  8. IP upgarde required

    Started by PMAYHEW, April 23rd, 2017 02:56 AM
    • Replies: 9
    • Views: 2,404
    November 11th, 2017, 11:25 AM Go to last post
  9. mSGDMA descriptor "repetition option" available?

    Started by Designer777, November 6th, 2017 07:49 AM
    • Replies: 0
    • Views: 79
    November 6th, 2017, 07:49 AM Go to last post
  10. Cyclone V Hard memory controller rate

    Started by Balasubrahmanya, May 14th, 2017 11:43 PM
    • Replies: 6
    • Views: 2,188
    November 6th, 2017, 12:39 AM Go to last post
    • Replies: 7
    • Views: 2,106
    November 6th, 2017, 12:32 AM Go to last post
  11. EMIF core clock sharing problem

    Started by Lzkzpl, June 22nd, 2017 06:51 AM
    • Replies: 3
    • Views: 926
    November 6th, 2017, 12:27 AM Go to last post
  12. DDR2 Fitter(Place & Route) report errors

    Started by jiangsuren, November 5th, 2017 07:46 PM
    • Replies: 2
    • Views: 192
    November 6th, 2017, 12:17 AM Go to last post
  13. 40 GbE on Arria10

    Started by robbio, March 21st, 2017 08:37 AM
    • Replies: 2
    • Views: 1,360
    November 1st, 2017, 06:33 PM Go to last post
  14. CVI overflow and CVO underflow

    Started by yuanmu0908, March 22nd, 2017 08:33 PM
    • Replies: 1
    • Views: 1,093
    November 1st, 2017, 06:29 PM Go to last post
  15. Using TSE with PCIe in a Linux enviroment

    Started by ChristH, October 16th, 2017 07:08 AM
    pcie tse linux
    • Replies: 3
    • Views: 476
    November 1st, 2017, 06:11 PM Go to last post
    • Replies: 5
    • Views: 1,999
    October 31st, 2017, 08:11 PM Go to last post
  16. Post Some trouble with HDMI RX ip core (Bitec IP core)

    Started by tiber, November 29th, 2016 06:53 PM
    hdmi rx core arria 10
    • Replies: 7
    • Views: 2,069
    October 31st, 2017, 02:58 AM Go to last post
  17. DDR3 RESET implementation overview

    Started by Drogio, November 3rd, 2016 06:17 AM
    • Replies: 2
    • Views: 827
    October 31st, 2017, 12:10 AM Go to last post
    • Replies: 3
    • Views: 669
    October 30th, 2017, 09:15 AM Go to last post
  18. Cyclone V Hard IP for PCIe

    Started by harys413, May 23rd, 2017 12:07 AM
    • Replies: 1
    • Views: 751
    October 30th, 2017, 01:48 AM Go to last post
  19. HMC simulation problem

    Started by stevecasselman, February 15th, 2017 05:05 PM
    altera_hmcc_mtaps_dcore, hmc
    • Replies: 2
    • Views: 740
    October 30th, 2017, 12:55 AM Go to last post
  20. Max10 speedgrade 8 and DDR2 memory

    Started by tfranke, January 23rd, 2017 05:05 AM
    • Replies: 1
    • Views: 666
    October 30th, 2017, 12:19 AM Go to last post
    • Replies: 2
    • Views: 595
    October 30th, 2017, 12:03 AM Go to last post
    • Replies: 1
    • Views: 921
    October 29th, 2017, 10:57 PM Go to last post
  21. Error with clock connections to DDR2

    Started by rod@ariradesign.com, September 20th, 2017 03:44 PM
    • Replies: 1
    • Views: 563
    October 29th, 2017, 10:49 PM Go to last post
    • Replies: 6
    • Views: 1,117
    October 29th, 2017, 10:29 PM Go to last post
  22. VIP SCALER II output data all zero

    Started by jiangsuren, October 19th, 2017 08:23 PM
    • Replies: 2
    • Views: 373
    October 29th, 2017, 08:46 PM Go to last post
  23. Hard IP for PCIe gen 3 simulation on Arria 10

    Started by sstrell, August 2nd, 2017 02:46 PM
    • Replies: 6
    • Views: 1,092
    October 25th, 2017, 06:24 AM Go to last post

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