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Forum: IP Discussion

A place to discuss topics related to Intellectual Property and solutions

  1. Sticky Thread Sticky: IP Core Resource Center for TSE, SDI, SPI4.2, PCIE, SRIO and 10GbE

    Started by GuruDog, September 24th, 2009 06:53 PM
    2 Pages
    1 2
    using tse ip core
    • Replies: 16
    • Views: 99,505
    June 9th, 2015, 07:50 AM Go to last post
  1. Parallel Flash Loader For MAX II .

    Started by RSK007, July 13th, 2018 10:58 AM
    pfl max ii
    • Replies: 3
    • Views: 242
    Yesterday, 06:53 PM Go to last post
  2. Arria 10 Transceiver PHY latency estimation

    Started by gusFring, Yesterday 10:12 AM
    • Replies: 0
    • Views: 82
    Yesterday, 10:12 AM Go to last post
  3. PCI-E DMA for Arria 10

    Started by wangzhihua445, July 17th, 2018 08:33 PM
    • Replies: 0
    • Views: 97
    July 17th, 2018, 08:33 PM Go to last post
  4. Question Third party LDPC ip Core

    Started by sunil.gupta@deal.drdo.in, July 16th, 2018 08:53 PM
    • Replies: 0
    • Views: 106
    July 16th, 2018, 08:53 PM Go to last post
  5. Triple Speed Ethernet (1000-Mbps) : transmit Jumbo frames?

    Started by mh9840, July 15th, 2018 04:21 AM
    jumbo frame, triple speed ethernet, tse
    • Replies: 0
    • Views: 134
    July 15th, 2018, 04:21 AM Go to last post
  6. DE1-SOC hps ddr3 memory

    Started by essaidia, July 12th, 2018 06:58 AM
    • Replies: 0
    • Views: 186
    July 12th, 2018, 06:58 AM Go to last post
    • Replies: 3
    • Views: 998
    July 12th, 2018, 02:26 AM Go to last post
  7. EMIF SDRAM Clock Domain Inquiry

    Started by mauriceyang, April 8th, 2018 06:38 PM
    emif, sdram
    • Replies: 4
    • Views: 811
    July 12th, 2018, 01:00 AM Go to last post
  8. Arria 10 - Reference Design - EMIF Timing Violations

    Started by aluamorim, July 4th, 2018 05:18 AM
    arria 10, ddr, emif, timing violations
    • Replies: 1
    • Views: 223
    July 12th, 2018, 12:47 AM Go to last post
  9. altera_dma driver PCIe under linux

    Started by ZECK, July 11th, 2018 07:23 AM
    • Replies: 0
    • Views: 141
    July 11th, 2018, 07:23 AM Go to last post
  10. UART IP - input clock

    Started by alin.dosa@microcimaging.c, July 7th, 2018 04:40 AM
    uart ip core clock
    • Replies: 1
    • Views: 229
    July 7th, 2018, 08:29 AM Go to last post
    • Replies: 0
    • Views: 183
    July 6th, 2018, 07:54 AM Go to last post
  11. Using ALTLVDS TX with changeable datarate

    Started by ana, July 6th, 2018 01:51 AM
    • Replies: 0
    • Views: 184
    July 6th, 2018, 01:51 AM Go to last post
  12. Cyclone 10 GX 10Gbps JESD204B

    Started by eplum, July 5th, 2018 11:00 PM
    • Replies: 0
    • Views: 183
    July 5th, 2018, 11:00 PM Go to last post
    • Replies: 3
    • Views: 372
    July 4th, 2018, 04:17 PM Go to last post
    • Replies: 0
    • Views: 206
    July 3rd, 2018, 05:56 AM Go to last post
  13. LPM Counter Output Resetting To Wrong Value

    Started by jlavie, June 27th, 2018 11:19 AM
    • Replies: 4
    • Views: 554
    June 28th, 2018, 10:50 AM Go to last post
  14. LVDS over CAT7 or CAT5 cables

    Started by Pavel_47, June 25th, 2018 02:35 PM
    • Replies: 1
    • Views: 318
    June 27th, 2018, 02:08 PM Go to last post
  15. Looking for Time Slot Interchange Digital Switch IP Core

    Started by lchamp, June 27th, 2018 06:25 AM
    digital, h.110, slot, switch, time
    • Replies: 0
    • Views: 246
    June 27th, 2018, 06:25 AM Go to last post
    • Replies: 6
    • Views: 686
    June 27th, 2018, 01:37 AM Go to last post
    • Replies: 1
    • Views: 292
    June 26th, 2018, 05:25 AM Go to last post
  16. Do I need pcie_reconfig_driver, pcie hardcore

    Started by eedude, February 4th, 2015 09:32 AM
    • Replies: 2
    • Views: 6,102
    June 26th, 2018, 04:49 AM Go to last post
  17. EMIF Toolkit create Memory Interface Connection problem

    Started by aabroug, June 22nd, 2018 05:42 AM
    • Replies: 2
    • Views: 500
    June 25th, 2018, 06:58 AM Go to last post
  18. Accessing DDR-Ram from FPGA on DE1-SoC

    Started by Cyano, April 10th, 2018 03:47 AM
    avalon-mm, ddr, hps, memory, verilog
    • Replies: 2
    • Views: 1,057
    June 21st, 2018, 12:31 AM Go to last post
  19. Cyclone V Hard Memory Controller MPFE bandwidth

    Started by simonkbrown, November 14th, 2017 06:55 AM
    cyclone, ddr, hmc, mpfe
    • Replies: 4
    • Views: 1,710
    June 20th, 2018, 01:57 PM Go to last post
  20. Arria 10 GX Dev Kit PCie DMA Timeout on a NUMA HPC

    Started by aluamorim, June 20th, 2018 07:22 AM
    dma, driver, numa, pcie
    • Replies: 0
    • Views: 304
    June 20th, 2018, 07:22 AM Go to last post
    • Replies: 3
    • Views: 2,278
    June 18th, 2018, 11:05 PM Go to last post
  21. avalon ST video protocol hard time

    Started by for(ever), June 18th, 2018 12:59 AM
    • Replies: 3
    • Views: 481
    June 18th, 2018, 05:17 AM Go to last post
  22. [Cyclone V PCIe Hard IP]: Avalon to PCIe read issue

    Started by Bhaumik, June 13th, 2018 02:48 AM
    • Replies: 4
    • Views: 717
    June 15th, 2018, 05:34 AM Go to last post
  23. MSGDMA Driver to do Host-to-Host DMAs

    Started by sjohnson, June 14th, 2018 05:12 AM
    host2host, jcjb, msgdma
    • Replies: 0
    • Views: 358
    June 14th, 2018, 05:12 AM Go to last post

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