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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Where to find Cyclone V Transciever Native PHY?

    Started by jtexas, Yesterday 07:21 AM
    • Replies: 1
    • Views: 73
    Yesterday, 06:24 PM Go to last post
  2. Fmax on Arria10 GX IO

    Started by spaul4, April 16th, 2018 11:18 PM
    • Replies: 1
    • Views: 118
    Yesterday, 05:51 PM Go to last post
  3. Why does Quartus schematic editor cut off text?

    Started by jh48, April 16th, 2018 07:38 AM
    • Replies: 6
    • Views: 1,249
    Yesterday, 09:16 AM Go to last post
  4. Need help identifying an FPGA board.

    Started by saint78, April 22nd, 2018 10:05 AM
    • Replies: 7
    • Views: 208
    April 23rd, 2018, 09:08 AM Go to last post
    • Replies: 5
    • Views: 123
    April 22nd, 2018, 09:47 PM Go to last post
    • Replies: 4
    • Views: 2,840
    April 20th, 2018, 09:21 PM Go to last post
  5. mSGDMA Transmission Data Missing

    Started by markZ123, April 12th, 2018 01:38 PM
    dma, msgdma, windows
    • Replies: 4
    • Views: 243
    April 20th, 2018, 07:11 AM Go to last post
  6. Configuration flash memory for Cyclone 10

    Started by DonskoyYuri, April 9th, 2018 08:01 AM
    • Replies: 2
    • Views: 271
    April 20th, 2018, 06:20 AM Go to last post
    • Replies: 4
    • Views: 159
    April 20th, 2018, 12:00 AM Go to last post
  7. VCXO removal in Stratix 10 E/H -tiles

    Started by jera, April 19th, 2018 10:37 PM
    • Replies: 0
    • Views: 115
    April 19th, 2018, 10:37 PM Go to last post
    • Replies: 1
    • Views: 134
    April 19th, 2018, 07:14 PM Go to last post
  8. Arrow Dual Boot from QSPI Flash Memory

    Started by PierreFLt, April 17th, 2018 04:23 AM
    • Replies: 1
    • Views: 104
    April 19th, 2018, 03:54 AM Go to last post
  9. Clock Constraints with PLL

    Started by konrad, April 19th, 2018 12:26 AM
    • Replies: 1
    • Views: 123
    April 19th, 2018, 12:35 AM Go to last post
  10. bbs prng simulation done, but no result waveform

    Started by vahnheng, April 17th, 2018 03:36 AM
    • Replies: 3
    • Views: 184
    April 18th, 2018, 08:25 PM Go to last post
  11. Cyclone V Configuration Devices

    Started by gj_leeson, October 14th, 2017 10:12 AM
    4 Pages
    1 2 3 ... 4
    • Replies: 39
    • Views: 8,472
    April 18th, 2018, 03:45 PM Go to last post
  12. cyclone 4 remote update

    Started by franticAF, April 18th, 2018 06:39 AM
    cyclone, remote, spi, update, watchdog
    • Replies: 0
    • Views: 111
    April 18th, 2018, 06:39 AM Go to last post
  13. How to solve silicon id error?

    Started by rockermr, April 17th, 2018 06:20 AM
    • Replies: 4
    • Views: 174
    April 18th, 2018, 01:05 AM Go to last post
  14. Marvell 88EE1111 PHY tranciever MDIO reg configuration

    Started by jsag, January 25th, 2017 01:34 PM
    4 Pages
    1 2 3 ... 4
    • Replies: 31
    • Views: 7,563
    April 17th, 2018, 04:44 PM Go to last post
  15. need help to read the register values

    Started by prasunaallu, April 17th, 2018 01:54 AM
    • Replies: 0
    • Views: 135
    April 17th, 2018, 01:54 AM Go to last post
  16. Intel HLS Compiler [Could not link 'vsim_auto_compile.so']

    Started by NZBRU, February 5th, 2018 03:24 PM
    • Replies: 3
    • Views: 576
    April 17th, 2018, 12:41 AM Go to last post
  17. DE10 Nano flash error

    Started by rockermr, April 16th, 2018 06:37 AM
    de10, flash, fpga, quartus prime, serial
    • Replies: 3
    • Views: 148
    April 16th, 2018, 06:10 PM Go to last post
  18. Windows 10 driver support for USB Blaster ?

    Started by dxpwny, May 23rd, 2017 05:19 PM
    2 Pages
    1 2
    blaster, windows 10
    • Replies: 12
    • Views: 6,414
    April 16th, 2018, 06:04 PM Go to last post
  19. Soc Verification concepts (Literature, Tools and Concepts)

    Started by RTLHLS, April 16th, 2018 04:26 AM
    • Replies: 2
    • Views: 175
    April 16th, 2018, 10:23 AM Go to last post
  20. Question SPI Slave Timing Constraint Question

    Started by ela05jdc, April 12th, 2018 08:08 AM
    • Replies: 5
    • Views: 227
    April 16th, 2018, 09:01 AM Go to last post
  21. Problem of using Altera Avalon-MM Master Template

    Started by alex-huang, April 15th, 2018 09:21 PM
    • Replies: 0
    • Views: 127
    April 15th, 2018, 09:21 PM Go to last post
    • Replies: 0
    • Views: 127
    April 15th, 2018, 09:42 AM Go to last post
    • Replies: 5
    • Views: 408
    April 14th, 2018, 05:02 AM Go to last post
  22. Cyclone V GT development board ethernet

    Started by shahzeb.khan@yongatek.com, April 13th, 2018 12:16 AM
    cyclonev, ethernet, pinout, tcp/ip
    • Replies: 0
    • Views: 166
    April 13th, 2018, 12:16 AM Go to last post
    • Replies: 0
    • Views: 148
    April 12th, 2018, 10:06 PM Go to last post
    • Replies: 4
    • Views: 3,444
    April 12th, 2018, 08:05 AM Go to last post

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