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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Computer configuration for FPGA compilation

    Started by valemea, February 22nd, 2018 02:58 PM
    • Replies: 5
    • Views: 208
    Yesterday, 02:18 AM Go to last post
  2. design simulation

    Started by ray_ba, February 21st, 2018 07:32 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 261
    February 23rd, 2018, 03:28 PM Go to last post
  3. Question Micron configuration flash replacement

    Started by foft, January 25th, 2018 01:26 PM
    configuration, epcq, epcqa, epcs, flash
    • Replies: 3
    • Views: 449
    February 23rd, 2018, 01:44 PM Go to last post
    • Replies: 8
    • Views: 348
    February 23rd, 2018, 01:40 PM Go to last post
  4. Excalibur family User's manual

    Started by tkleman, February 22nd, 2018 07:00 AM
    documentation, epxa4f672c1, excalibur, manual, pdf
    • Replies: 4
    • Views: 117
    February 23rd, 2018, 12:32 PM Go to last post
  5. Lightbulb Avalon interface verification problem

    Started by punno2015, February 23rd, 2018 02:53 AM
    • Replies: 1
    • Views: 88
    February 23rd, 2018, 12:21 PM Go to last post
  6. Effect of nCE (Chip Enable)

    Started by BernhardB, February 22nd, 2018 02:57 AM
    chip enable, nce, user mode
    • Replies: 5
    • Views: 165
    February 23rd, 2018, 09:00 AM Go to last post
  7. FPP Configuration, Bank 2A and reuse

    Started by BernhardB, February 21st, 2018 07:43 AM
    bank 2a, flash, fpp configuration, nce, parallel interface
    • Replies: 2
    • Views: 123
    February 23rd, 2018, 04:01 AM Go to last post
  8. License issue with Quartus II 6.0

    Started by sashient@sashient.com, February 22nd, 2018 05:20 PM
    • Replies: 1
    • Views: 88
    February 23rd, 2018, 12:28 AM Go to last post
  9. Intel HLS (High Level Synthesis) compiler

    Started by BKN, January 8th, 2018 08:09 AM
    • Replies: 1
    • Views: 382
    February 22nd, 2018, 10:45 PM Go to last post
  10. Cyclone II , Fifo UART, Nios II

    Started by Faeren0327, February 22nd, 2018 12:06 PM
    • Replies: 0
    • Views: 87
    February 22nd, 2018, 12:06 PM Go to last post
  11. Unconstrained paths in timequest result in setup violation

    Started by VijeyShankar, February 21st, 2018 10:46 AM
    • Replies: 3
    • Views: 145
    February 22nd, 2018, 08:39 AM Go to last post
  12. Fractional N PLL implimentation in IP possible on Cyclone V and max10?

    Started by BillyZDSP, February 13th, 2018 09:00 PM
    2 Pages
    1 2
    • Replies: 16
    • Views: 527
    February 21st, 2018, 12:58 PM Go to last post
  13. Can I use MAX3000 in Quartus lite 17.1

    Started by wogoos, February 21st, 2018 09:59 AM
    max3000, quartus17.1
    • Replies: 1
    • Views: 96
    February 21st, 2018, 10:37 AM Go to last post
    • Replies: 6
    • Views: 1,870
    February 21st, 2018, 07:56 AM Go to last post
    • Replies: 2
    • Views: 170
    February 21st, 2018, 12:50 AM Go to last post
  14. Internal Error: Sub-system: QIS File ....

    Started by dbanks12, February 7th, 2018 01:55 PM
    • Replies: 2
    • Views: 291
    February 20th, 2018, 06:14 PM Go to last post
  15. Issues with PLL's in Cyclone V SoC

    Started by sudhee2893, February 20th, 2018 12:36 PM
    • Replies: 0
    • Views: 127
    February 20th, 2018, 12:36 PM Go to last post
    • Replies: 0
    • Views: 117
    February 19th, 2018, 11:02 PM Go to last post
  16. PLL's in Cyclone V

    Started by sudhee2893, February 10th, 2018 06:19 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 661
    February 18th, 2018, 06:06 PM Go to last post
  17. Increase DDR RAM of FPGA

    Started by gudurvy, June 23rd, 2017 09:41 AM
    • Replies: 3
    • Views: 1,125
    February 17th, 2018, 06:03 PM Go to last post
  18. Altera DE2 read input from a weight sensor's HX711 ADC

    Started by lingyueqing, January 18th, 2018 12:26 AM
    • Replies: 2
    • Views: 254
    February 17th, 2018, 05:39 PM Go to last post
    • Replies: 0
    • Views: 194
    February 17th, 2018, 03:34 PM Go to last post
  19. Question FPGA (Cyclone IV E) new project after a long break

    Started by Rysiu, February 16th, 2018 05:11 PM
    • Replies: 3
    • Views: 272
    February 16th, 2018, 05:31 PM Go to last post
  20. Quartus can't find shared library

    Started by marion, February 27th, 2012 07:16 PM
    • Replies: 8
    • Views: 37,263
    February 16th, 2018, 10:47 AM Go to last post
  21. I need help with marking EP1K100QI208-2N

    Started by Egor, February 15th, 2018 10:26 PM
    case, ep1k100qi208-2n, marking, mold gate, roman numerals
    • Replies: 0
    • Views: 165
    February 15th, 2018, 10:26 PM Go to last post
  22. My FPGA design looking for new home.. Altera FPGA?

    Started by BillyZDSP, February 9th, 2018 01:56 PM
    • Replies: 4
    • Views: 300
    February 15th, 2018, 04:08 PM Go to last post
  23. PowerSOC device P/N EN6362QI Package Outline Drawing Request

    Started by Edward, February 15th, 2018 12:29 PM
    • Replies: 0
    • Views: 152
    February 15th, 2018, 12:29 PM Go to last post
  24. Is there a Qsys IP that can read/write SD Card via HAL?

    Started by XAUI, February 13th, 2018 08:02 AM
    • Replies: 1
    • Views: 200
    February 15th, 2018, 05:36 AM Go to last post
  25. Linux DMA driver for Altera

    Started by prito, February 14th, 2018 02:26 AM
    • Replies: 2
    • Views: 217
    February 15th, 2018, 02:06 AM Go to last post

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