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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Altera mm interconnect

    Started by MUTHUVENKATESH, Today 01:59 AM
    • Replies: 0
    • Views: 12
    Today, 01:59 AM Go to last post
  2. Altera_mm_interconnect functionality

    Started by MUTHUVENKATESH, Yesterday 03:37 AM
    • Replies: 2
    • Views: 93
    Yesterday, 09:34 PM Go to last post
  3. Unhappy Problems logging into myAltera

    Started by SimonJRichter, March 6th, 2017 08:09 AM
    myaltera
    • Replies: 5
    • Views: 776
    September 17th, 2017, 11:02 PM Go to last post
    • Replies: 1
    • Views: 181
    September 17th, 2017, 06:56 PM Go to last post
    • Replies: 8
    • Views: 745
    September 17th, 2017, 10:45 AM Go to last post
  4. Question TSE & PHY configuration problem

    Started by ghazis, September 13th, 2017 10:40 PM
    • Replies: 2
    • Views: 198
    September 17th, 2017, 12:38 AM Go to last post
  5. Information needed for slave addressing from master...

    Started by MUTHUVENKATESH, September 15th, 2017 12:36 AM
    • Replies: 0
    • Views: 123
    September 15th, 2017, 12:36 AM Go to last post
  6. Problem with sending data by EP through PCIe switch

    Started by ipruzhinin, September 14th, 2017 12:54 AM
    • Replies: 0
    • Views: 145
    September 14th, 2017, 12:54 AM Go to last post
  7. Post Query regarding Simulation in Modelsim

    Started by tejas.limbasiya, September 12th, 2017 10:36 PM
    • Replies: 4
    • Views: 269
    September 13th, 2017, 04:11 AM Go to last post
  8. Unhappy So frustrated about the implementation of SGMII

    Started by peter.chang, September 12th, 2017 11:28 PM
    • Replies: 0
    • Views: 148
    September 12th, 2017, 11:28 PM Go to last post
  9. Burst transfer from Avalon MM Master BFM

    Started by VijeyShankar, September 11th, 2017 06:37 AM
    • Replies: 0
    • Views: 185
    September 11th, 2017, 06:37 AM Go to last post
  10. Eclipse locks jtag

    Started by jsgn3, September 11th, 2017 05:18 AM
    • Replies: 0
    • Views: 161
    September 11th, 2017, 05:18 AM Go to last post
  11. altera.com problems?

    Started by petter, September 9th, 2017 02:53 AM
    • Replies: 4
    • Views: 321
    September 9th, 2017, 10:15 PM Go to last post
  12. Cyclone V SoC Development Kit

    Started by th_altera_forum, August 18th, 2017 06:10 PM
    • Replies: 2
    • Views: 461
    September 8th, 2017, 01:27 PM Go to last post
    • Replies: 6
    • Views: 478
    September 8th, 2017, 05:26 AM Go to last post
  13. make: *** [my_hello_world.elf] Error 1

    Started by ryan.reas, September 4th, 2015 05:19 PM
    • Replies: 5
    • Views: 5,662
    September 7th, 2017, 06:00 AM Go to last post
  14. Burst count limit avalon master bfm

    Started by MUTHUVENKATESH, September 7th, 2017 05:36 AM
    • Replies: 0
    • Views: 201
    September 7th, 2017, 05:36 AM Go to last post
  15. Newbie needs help please

    Started by marcusnicolas, September 4th, 2017 08:06 AM
    • Replies: 6
    • Views: 589
    September 5th, 2017, 06:36 PM Go to last post
  16. Elf-file stops loading just before InterNiche message

    Started by jsgn3, September 4th, 2017 02:21 AM
    elf-file, tse license
    • Replies: 0
    • Views: 261
    September 4th, 2017, 02:21 AM Go to last post
  17. What do you think most popular usage of FPGA?

    Started by rlawhdgus34, August 27th, 2017 07:00 AM
    asic, fpga, fpga usage, industry
    • Replies: 4
    • Views: 632
    September 1st, 2017, 12:06 PM Go to last post
  18. Altera's LPDDR3/4 Supported Reference Board

    Started by sheladiya_vijay, August 30th, 2017 11:35 PM
    • Replies: 2
    • Views: 385
    September 1st, 2017, 03:15 AM Go to last post
  19. Marvell 88EE1111 PHY tranciever MDIO reg configuration

    Started by jsag, January 25th, 2017 01:34 PM
    2 Pages
    1 2
    • Replies: 19
    • Views: 3,123
    August 31st, 2017, 01:31 PM Go to last post
  20. Programming Issue with Active Serial Programming

    Started by BlairH, August 29th, 2017 08:16 AM
    cyclone, fpga, programming
    • Replies: 7
    • Views: 726
    August 31st, 2017, 08:17 AM Go to last post
  21. System doesn't keep programming

    Started by enlijoe, August 28th, 2017 08:12 PM
    max10, programming
    • Replies: 6
    • Views: 658
    August 29th, 2017, 10:05 AM Go to last post
    • Replies: 2
    • Views: 605
    August 29th, 2017, 06:36 AM Go to last post
  22. UART RS232 connection between Matlab and NiosII

    Started by shameem1189, August 24th, 2017 02:18 PM
    rs232
    • Replies: 0
    • Views: 422
    August 24th, 2017, 02:18 PM Go to last post
  23. Quartus Prime Lite Edition Clock

    Started by gamzecabadag, August 24th, 2017 12:17 AM
    • Replies: 4
    • Views: 547
    August 24th, 2017, 09:13 AM Go to last post
  24. Don't see Inbox - Messaging

    Started by rainbow, August 24th, 2017 02:41 AM
    • Replies: 1
    • Views: 372
    August 24th, 2017, 06:17 AM Go to last post
  25. 7 Segment display

    Started by marcusnicolas, August 22nd, 2017 09:09 PM
    • Replies: 4
    • Views: 508
    August 24th, 2017, 05:04 AM Go to last post
  26. Question Referent Clock PCIe

    Started by sxmg92, August 23rd, 2017 08:36 PM
    cyclone v, lanes, pcie
    • Replies: 0
    • Views: 310
    August 23rd, 2017, 08:36 PM Go to last post

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