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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Program EPM7064 to match EPS464

    Started by jrippin, October 16th, 2017 01:24 PM
    epm7064, eps464
    • Replies: 4
    • Views: 102
    Yesterday, 11:03 PM Go to last post
  2. nested loop error in OpenCL hardware run

    Started by Lancerchiang, Yesterday 02:31 AM
    hardware, loop, opencl, quartus, simulation
    • Replies: 3
    • Views: 83
    Yesterday, 07:59 PM Go to last post
  3. Using Byte Blaster Rev. C with FTDI232RL breakout board

    Started by XAUI, October 16th, 2017 05:48 PM
    • Replies: 0
    • Views: 58
    October 16th, 2017, 05:48 PM Go to last post
    • Replies: 0
    • Views: 52
    October 16th, 2017, 02:00 PM Go to last post
  4. Implementation of VHDL program on FPGA

    Started by berkoka, October 15th, 2017 09:21 AM
    • Replies: 8
    • Views: 203
    October 16th, 2017, 12:10 PM Go to last post
  5. Cyclone V Configuration Devices

    Started by gj_leeson, October 14th, 2017 10:12 AM
    • Replies: 2
    • Views: 153
    October 16th, 2017, 09:52 AM Go to last post
  6. EPCS Discontinuation, looking for replacement.

    Started by BhavaniT, September 22nd, 2017 07:42 AM
    • Replies: 5
    • Views: 670
    October 16th, 2017, 01:29 AM Go to last post
    • Replies: 2
    • Views: 296
    October 15th, 2017, 07:21 PM Go to last post
  7. Cyclone V Transceiver Backplane Support

    Started by joe306, October 4th, 2017 02:11 PM
    • Replies: 2
    • Views: 276
    October 15th, 2017, 07:18 PM Go to last post
  8. Building Quartus16.1 files on Quartus 16.0

    Started by jeebujacob, October 9th, 2017 02:30 AM
    quartus, timingclosure
    • Replies: 5
    • Views: 278
    October 15th, 2017, 07:14 PM Go to last post
  9. Lightbulb Programming cyclone III & IV using a custom USB Blaster

    Started by DavidR, October 27th, 2015 06:08 AM
    blaster, configuration, cyclone, ftdi
    • Replies: 7
    • Views: 3,035
    October 14th, 2017, 11:42 PM Go to last post
  10. Question PCIE Pinout doubts and Problems Cyclone V

    Started by sxmg92, October 14th, 2017 11:29 AM
    pcie, pinouts
    • Replies: 0
    • Views: 109
    October 14th, 2017, 11:29 AM Go to last post
  11. Footprint for UBGA 324 pin package

    Started by rod@ariradesign.com, October 11th, 2017 04:30 PM
    • Replies: 6
    • Views: 281
    October 14th, 2017, 03:04 AM Go to last post
  12. Post Noise decoupling

    Started by shipra7993, October 13th, 2017 11:10 PM
    • Replies: 0
    • Views: 108
    October 13th, 2017, 11:10 PM Go to last post
  13. Exclamation Hardware run result does no match with simulation

    Started by Lancerchiang, October 13th, 2017 12:55 AM
    hardware, opencl, quartus, simulation
    • Replies: 2
    • Views: 182
    October 13th, 2017, 08:34 AM Go to last post
  14. Cyclone V E Instantiating Multiple ASMI Blocks

    Started by polson, October 11th, 2017 07:46 AM
    • Replies: 0
    • Views: 154
    October 11th, 2017, 07:46 AM Go to last post
  15. Cannot generate cof file - Quartus Prime Lite V17 (595)

    Started by Cluso99, October 9th, 2017 09:35 PM
    • Replies: 2
    • Views: 211
    October 10th, 2017, 02:27 PM Go to last post
  16. Cyclone V SoC Development Kit

    Started by th_altera_forum, August 18th, 2017 06:10 PM
    • Replies: 5
    • Views: 869
    October 10th, 2017, 12:53 PM Go to last post
  17. Angry Cannot login properly to myAltera

    Started by qu1j0t3, October 7th, 2017 02:21 PM
    • Replies: 9
    • Views: 1,265
    October 9th, 2017, 07:47 PM Go to last post
  18. Teraisc DE0-CV (Cyclone V) programming error

    Started by yileku, October 8th, 2017 10:25 AM
    • Replies: 1
    • Views: 198
    October 9th, 2017, 10:10 AM Go to last post
  19. Post sof file not updated

    Started by mrbenzalot, October 9th, 2017 05:58 AM
    • Replies: 0
    • Views: 164
    October 9th, 2017, 05:58 AM Go to last post
  20. project compilation is taking forever to finish

    Started by Lancerchiang, October 8th, 2017 05:45 PM
    compilation, opencl, quartus, synthesis
    • Replies: 3
    • Views: 269
    October 9th, 2017, 12:55 AM Go to last post
  21. Quartus II and Altera Usb Blaster

    Started by mustafayilmaz, October 8th, 2017 09:50 AM
    • Replies: 1
    • Views: 190
    October 8th, 2017, 11:45 AM Go to last post
  22. Video memory scheme?

    Started by Pickwick, October 6th, 2017 09:27 AM
    • Replies: 1
    • Views: 247
    October 6th, 2017, 02:07 PM Go to last post
  23. DE0-Nano-SoC: How HPS(ARM) recognizes f2h_irq0 or f2h_irq1 interrupts from FPGA

    Started by sebar, January 16th, 2016 09:41 AM
    2 Pages
    1 2
    • Replies: 14
    • Views: 3,823
    October 6th, 2017, 09:30 AM Go to last post
    • Replies: 1
    • Views: 247
    October 6th, 2017, 05:02 AM Go to last post
  24. Can not reprogram the FPGA/JTAG does not respond

    Started by tamzidul, September 29th, 2017 11:31 AM
    • Replies: 2
    • Views: 366
    October 3rd, 2017, 12:48 AM Go to last post
  25. help for audio codec using VHDL

    Started by bhatta422, November 10th, 2010 09:42 AM
    8 Pages
    1 2 3 ... 8
    • Replies: 72
    • Views: 115,367
    October 2nd, 2017, 01:40 AM Go to last post
  26. Booting from the QSPI flash

    Started by bwasim, September 29th, 2017 03:53 PM
    cyclonev, nor flash, qspi
    • Replies: 0
    • Views: 286
    September 29th, 2017, 03:53 PM Go to last post
  27. Port number limitation prevents my codes from compiling

    Started by bin9000, September 27th, 2017 05:10 PM
    • Replies: 9
    • Views: 815
    September 29th, 2017, 01:35 PM Go to last post

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