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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. Quartus Prime Pro: Internal Error: Sub-system: SUTIL

    Started by Terry.Fan, November 19th, 2017 06:41 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 339
    Yesterday, 08:32 PM Go to last post
  2. triple-speed internet and RTL8211

    Started by jiangjiqiang, November 22nd, 2017 11:57 PM
    • Replies: 0
    • Views: 83
    November 22nd, 2017, 11:57 PM Go to last post
  3. Exclamation Fitter Error with LOANER option on cyclone V

    Started by eivann, November 12th, 2017 06:28 PM
    cyclone v, hps, loaner, pins, tcl scrips
    • Replies: 4
    • Views: 230
    November 22nd, 2017, 10:54 PM Go to last post
  4. i want to get some information of EP3C40Q240C8N

    Started by amanda, August 7th, 2016 07:26 PM
    • Replies: 1
    • Views: 619
    November 22nd, 2017, 08:00 PM Go to last post
    • Replies: 2
    • Views: 261
    November 22nd, 2017, 04:09 PM Go to last post
  5. Question Getting Started with OpenCL Programming on FPGA

    Started by oasiskiwi, November 17th, 2017 01:59 PM
    altera, fpga, intel, opencl
    • Replies: 2
    • Views: 206
    November 22nd, 2017, 08:49 AM Go to last post
  6. Trojan horse on Quartus II 12.1 SP1

    Started by AAF, November 22nd, 2017 08:17 AM
    • Replies: 0
    • Views: 78
    November 22nd, 2017, 08:17 AM Go to last post
  7. Post Reset for PLL

    Started by Nagakiran, November 22nd, 2015 08:38 PM
    2 Pages
    1 2
    pll, reset
    • Replies: 11
    • Views: 4,296
    November 22nd, 2017, 07:12 AM Go to last post
  8. Cyclone V Configuration Devices

    Started by gj_leeson, October 14th, 2017 11:12 AM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 1,837
    November 21st, 2017, 11:40 PM Go to last post
  9. DSP Builder

    Started by saba_y, November 21st, 2017 07:55 AM
    • Replies: 0
    • Views: 70
    November 21st, 2017, 07:55 AM Go to last post
  10. No logic elements although I have an output

    Started by phd.taha, November 16th, 2017 07:54 AM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 740
    November 21st, 2017, 06:21 AM Go to last post
  11. Where to find SONET-SDH Compiler?

    Started by sri.cvcblr, November 20th, 2017 11:13 PM
    compiler, sdh, sonet
    • Replies: 2
    • Views: 106
    November 21st, 2017, 12:58 AM Go to last post
  12. PCI Express Avalon-MM DMA Windows Source Code?

    Started by PPTim, November 14th, 2017 11:35 AM
    • Replies: 1
    • Views: 206
    November 21st, 2017, 12:00 AM Go to last post
    • Replies: 0
    • Views: 67
    November 20th, 2017, 11:01 PM Go to last post
  13. Stratix 10 PCIe Configuration Register Access

    Started by AndyN, November 20th, 2017 03:04 PM
    • Replies: 0
    • Views: 94
    November 20th, 2017, 03:04 PM Go to last post
  14. Network Big Data Transfer Limitations

    Started by FINCH1, November 20th, 2017 06:12 AM
    big data, network
    • Replies: 0
    • Views: 117
    November 20th, 2017, 06:12 AM Go to last post
  15. Arria 10 auto configuration issue with EPCQ-L

    Started by tetsuya, November 9th, 2017 05:56 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 659
    November 19th, 2017, 11:57 PM Go to last post
  16. Unhappy SignalTap different sample depth led to different logic

    Started by c89412564, November 16th, 2017 06:37 PM
    14.1, signaltap
    • Replies: 7
    • Views: 363
    November 17th, 2017, 02:00 PM Go to last post
    • Replies: 3
    • Views: 341
    November 17th, 2017, 01:11 AM Go to last post
  17. Cyclone V and Gate Level Simulation

    Started by xwalker, November 29th, 2015 10:03 AM
    • Replies: 8
    • Views: 2,459
    November 16th, 2017, 10:30 AM Go to last post
  18. Cyclone V E Development Board Kit

    Started by john_altera, November 15th, 2017 04:33 PM
    • Replies: 6
    • Views: 338
    November 16th, 2017, 09:17 AM Go to last post
  19. EMIF oct_rzqin compile error!

    Started by Terry.Fan, November 15th, 2017 07:56 AM
    • Replies: 2
    • Views: 211
    November 15th, 2017, 07:38 PM Go to last post
  20. Cyclone 10 GX LVDS clock buffer

    Started by Y0tsuya, November 15th, 2017 04:49 PM
    • Replies: 0
    • Views: 140
    November 15th, 2017, 04:49 PM Go to last post
  21. how to simulate NIOS II generated in Qsys_Pro v17.0

    Started by Terry.Fan, November 8th, 2017 12:16 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 563
    November 15th, 2017, 03:21 AM Go to last post
  22. Hex Values on LCD Display

    Started by vrndandu, November 14th, 2017 06:47 PM
    • Replies: 0
    • Views: 135
    November 14th, 2017, 06:47 PM Go to last post
  23. 1.5V PCML to CML interface

    Started by maurizio76, November 14th, 2017 01:20 AM
    altgx, cml, pcml
    • Replies: 2
    • Views: 222
    November 14th, 2017, 04:26 AM Go to last post
  24. Quartus programmer software for 32-bit PC

    Started by reimonag, November 13th, 2017 12:34 AM
    • Replies: 4
    • Views: 253
    November 14th, 2017, 12:10 AM Go to last post
    • Replies: 1
    • Views: 182
    November 13th, 2017, 11:42 PM Go to last post
  25. 385 jtag adapter board

    Started by bavab, November 5th, 2017 03:32 AM
    adapter board, jatag
    • Replies: 3
    • Views: 362
    November 13th, 2017, 10:57 AM Go to last post
    • Replies: 0
    • Views: 129
    November 13th, 2017, 09:03 AM Go to last post

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