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Forum: General Altera Discussion

A place to discuss topics on general Altera products, applications and development

  1. design simulation

    Started by ray_ba, Yesterday 07:32 AM
    • Replies: 4
    • Views: 68
    Today, 12:29 AM Go to last post
  2. Fractional N PLL implimentation in IP possible on Cyclone V and max10?

    Started by BillyZDSP, February 13th, 2018 09:00 PM
    2 Pages
    1 2
    • Replies: 16
    • Views: 418
    Yesterday, 12:58 PM Go to last post
    • Replies: 1
    • Views: 48
    Yesterday, 11:30 AM Go to last post
  3. Can I use MAX3000 in Quartus lite 17.1

    Started by wogoos, Yesterday 09:59 AM
    max3000, quartus17.1
    • Replies: 1
    • Views: 42
    Yesterday, 10:37 AM Go to last post
    • Replies: 6
    • Views: 1,807
    Yesterday, 07:56 AM Go to last post
  4. FPP Configuration, Bank 2A and reuse

    Started by BernhardB, Yesterday 07:43 AM
    bank 2a, flash, fpp configuration, nce, parallel interface
    • Replies: 0
    • Views: 36
    Yesterday, 07:43 AM Go to last post
    • Replies: 2
    • Views: 114
    Yesterday, 12:50 AM Go to last post
  5. Internal Error: Sub-system: QIS File ....

    Started by dbanks12, February 7th, 2018 01:55 PM
    • Replies: 2
    • Views: 233
    February 20th, 2018, 06:14 PM Go to last post
  6. Issues with PLL's in Cyclone V SoC

    Started by sudhee2893, February 20th, 2018 12:36 PM
    • Replies: 0
    • Views: 90
    February 20th, 2018, 12:36 PM Go to last post
  7. Angry Arria10 SoC, Angstrom Packge manager opkg issues!!

    Started by ifarhat, February 20th, 2018 02:49 AM
    arria10 soc, gcc, linux angstrom, opkg, pkg-config
    • Replies: 0
    • Views: 88
    February 20th, 2018, 02:49 AM Go to last post
    • Replies: 0
    • Views: 87
    February 19th, 2018, 11:02 PM Go to last post
  8. PLL's in Cyclone V

    Started by sudhee2893, February 10th, 2018 06:19 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 569
    February 18th, 2018, 06:06 PM Go to last post
  9. Increase DDR RAM of FPGA

    Started by gudurvy, June 23rd, 2017 09:41 AM
    • Replies: 3
    • Views: 1,061
    February 17th, 2018, 06:03 PM Go to last post
  10. Altera DE2 read input from a weight sensor's HX711 ADC

    Started by lingyueqing, January 18th, 2018 12:26 AM
    • Replies: 2
    • Views: 198
    February 17th, 2018, 05:39 PM Go to last post
    • Replies: 0
    • Views: 149
    February 17th, 2018, 03:34 PM Go to last post
  11. Question FPGA (Cyclone IV E) new project after a long break

    Started by Rysiu, February 16th, 2018 05:11 PM
    • Replies: 3
    • Views: 196
    February 16th, 2018, 05:31 PM Go to last post
  12. Quartus can't find shared library

    Started by marion, February 27th, 2012 07:16 PM
    • Replies: 8
    • Views: 37,189
    February 16th, 2018, 10:47 AM Go to last post
  13. I need help with marking EP1K100QI208-2N

    Started by Egor, February 15th, 2018 10:26 PM
    case, ep1k100qi208-2n, marking, mold gate, roman numerals
    • Replies: 0
    • Views: 131
    February 15th, 2018, 10:26 PM Go to last post
  14. My FPGA design looking for new home.. Altera FPGA?

    Started by BillyZDSP, February 9th, 2018 01:56 PM
    • Replies: 4
    • Views: 252
    February 15th, 2018, 04:08 PM Go to last post
  15. PowerSOC device P/N EN6362QI Package Outline Drawing Request

    Started by Edward, February 15th, 2018 12:29 PM
    • Replies: 0
    • Views: 118
    February 15th, 2018, 12:29 PM Go to last post
  16. Is there a Qsys IP that can read/write SD Card via HAL?

    Started by XAUI, February 13th, 2018 08:02 AM
    • Replies: 1
    • Views: 168
    February 15th, 2018, 05:36 AM Go to last post
  17. Linux DMA driver for Altera

    Started by prito, February 14th, 2018 02:26 AM
    • Replies: 2
    • Views: 171
    February 15th, 2018, 02:06 AM Go to last post
  18. Access Point for Intel Wifi Module

    Started by kiran.m, February 15th, 2018 01:43 AM
    • Replies: 0
    • Views: 113
    February 15th, 2018, 01:43 AM Go to last post
  19. 5.8GHz PLL output from Cyclone V?

    Started by rGlennCii, February 13th, 2018 01:49 PM
    • Replies: 3
    • Views: 226
    February 14th, 2018, 11:54 AM Go to last post
  20. BSP Generation Error

    Started by dgajudo, May 27th, 2012 09:33 PM
    • Replies: 5
    • Views: 32,832
    February 14th, 2018, 04:59 AM Go to last post
  21. Socket server design on Arria 10 GX FPGA board?

    Started by legionexl, February 12th, 2018 12:28 PM
    arria 10, socket server
    • Replies: 0
    • Views: 143
    February 12th, 2018, 12:28 PM Go to last post
    • Replies: 2
    • Views: 353
    February 12th, 2018, 12:44 AM Go to last post
    • Replies: 2
    • Views: 210
    February 10th, 2018, 02:28 PM Go to last post
  22. Exclamation i need a sdc file!!

    Started by eivann, February 8th, 2018 03:44 PM
    clock, cyclone v, hps, loaner, sdc file
    • Replies: 2
    • Views: 309
    February 9th, 2018, 12:31 PM Go to last post
    • Replies: 3
    • Views: 230
    February 8th, 2018, 03:07 PM Go to last post

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