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Forum: DSP Builder and DSP IPs

A place to discuss topics related to DSP Builder and DSP IP cores

  1. How to force a mode onto a Stratix V DSP block?

    Started by jpt, December 1st, 2017 05:45 AM
    dsp, multipliers, stratix v
    • Replies: 0
    • Views: 398
    December 1st, 2017, 05:45 AM Go to last post
  2. Unhappy Adding output signals to DSP Builder exp conduit

    Started by zdrake, November 17th, 2017 01:59 PM
    conduit, data_out, exp, output, signals
    • Replies: 2
    • Views: 720
    November 28th, 2017, 03:16 PM Go to last post
  3. Simple MegaCore FFT Simulink Model

    Started by milruwan, November 7th, 2017 12:03 PM
    • Replies: 0
    • Views: 595
    November 7th, 2017, 12:03 PM Go to last post
    • Replies: 2
    • Views: 2,528
    October 25th, 2017, 03:14 AM Go to last post
  4. FFT MegaCore RAM allocation

    Started by roger8144, December 21st, 2016 02:06 PM
    • Replies: 1
    • Views: 1,961
    October 25th, 2017, 02:57 AM Go to last post
  5. How to improve timing in FIR Compiler II?

    Started by Kippis, April 27th, 2017 06:27 AM
    • Replies: 1
    • Views: 1,887
    October 19th, 2017, 02:07 AM Go to last post
  6. Multiply Accumulate in dsp builder advanced blocksets

    Started by VKT_ZN, August 2nd, 2017 07:04 AM
    • Replies: 1
    • Views: 1,213
    October 19th, 2017, 01:37 AM Go to last post
  7. FFT Megacore sink_ready never goes to 1

    Started by winter1894, January 7th, 2016 08:25 PM
    • Replies: 3
    • Views: 2,408
    October 19th, 2017, 01:25 AM Go to last post
  8. Lightbulb Altera FIR Compiler II 15.0 Coefficients Reload Issues

    Started by TCWORLD, July 12th, 2017 04:41 PM
    bug, fir
    • Replies: 0
    • Views: 1,102
    July 12th, 2017, 04:41 PM Go to last post
  9. ALtera FFT Outputs in SignalTapII

    Started by new_user, May 17th, 2017 02:12 PM
    • Replies: 1
    • Views: 2,101
    May 18th, 2017, 07:35 AM Go to last post
    • Replies: 1
    • Views: 2,047
    April 21st, 2017, 12:15 AM Go to last post
    • Replies: 1
    • Views: 1,547
    April 20th, 2017, 03:12 AM Go to last post
  10. Hardware In The Loop

    Started by sirbabak, April 18th, 2017 06:14 AM
    dsp builer, fil, hil, sil
    • Replies: 1
    • Views: 1,490
    April 19th, 2017, 07:09 AM Go to last post
  11. Arria V Gx development kit RF

    Started by Samantha, March 31st, 2017 10:32 PM
    • Replies: 0
    • Views: 1,568
    March 31st, 2017, 10:32 PM Go to last post
  12. FFT Megafunction v12.0 issues

    Started by roger8144, March 15th, 2017 08:38 AM
    • Replies: 4
    • Views: 2,760
    March 15th, 2017, 12:00 PM Go to last post
  13. Exclamation MegaCore Function Generation Error

    Started by weikunhou, November 15th, 2016 01:12 PM
    • Replies: 1
    • Views: 2,373
    March 7th, 2017, 12:32 PM Go to last post
  14. CIC Megacore Function

    Started by arianerafael, March 3rd, 2017 12:02 PM
    • Replies: 0
    • Views: 1,593
    March 3rd, 2017, 12:02 PM Go to last post
  15. Clock_Derivered Bock Problem

    Started by arianerafael, December 16th, 2016 06:23 AM
    • Replies: 1
    • Views: 2,024
    March 3rd, 2017, 08:23 AM Go to last post
    • Replies: 7
    • Views: 2,873
    February 22nd, 2017, 02:59 AM Go to last post
  16. Precise sampling rate and decimation

    Started by neurotek1, February 21st, 2017 02:07 PM
    • Replies: 3
    • Views: 2,623
    February 22nd, 2017, 12:49 AM Go to last post
    • Replies: 1
    • Views: 2,157
    February 11th, 2017, 04:16 AM Go to last post
  17. Resource usage for Arria 10 DSP performing Multiply Add

    Started by boddis, January 20th, 2017 05:43 AM
    • Replies: 1
    • Views: 1,976
    January 20th, 2017, 05:55 AM Go to last post
  18. create custom component

    Started by sirbabak, January 9th, 2017 06:33 AM
    • Replies: 0
    • Views: 1,722
    January 9th, 2017, 06:33 AM Go to last post
  19. FFT MegaCore 13.0 Generation Stuck

    Started by roger8144, December 8th, 2016 07:16 AM
    • Replies: 5
    • Views: 3,662
    December 29th, 2016, 04:00 AM Go to last post
  20. Quartus II Web Edition and Altera IP

    Started by Palmen, June 7th, 2012 03:27 AM
    • Replies: 4
    • Views: 40,166
    December 29th, 2016, 03:54 AM Go to last post
  21. Real time FIR filtering MAX 10 FPGA Development Board

    Started by tan28, November 4th, 2016 09:02 AM
    • Replies: 7
    • Views: 3,852
    November 4th, 2016, 11:23 AM Go to last post
  22. viterbi IP core problem

    Started by yhaokai, October 26th, 2016 07:43 AM
    • Replies: 0
    • Views: 1,738
    October 26th, 2016, 07:43 AM Go to last post
  23. QSYS FFT 16.0 issue

    Started by samuel.lehner.proceq, October 18th, 2016 01:58 AM
    • Replies: 1
    • Views: 2,409
    October 21st, 2016, 06:37 AM Go to last post
  24. Issue with CIC filter implementation using DSP builder.

    Started by swarnava9, September 12th, 2016 10:43 AM
    • Replies: 8
    • Views: 4,566
    September 13th, 2016, 03:11 PM Go to last post
  25. Black Box and SIMULINK Model

    Started by shauk, September 2nd, 2016 12:26 AM
    • Replies: 0
    • Views: 2,320
    September 2nd, 2016, 12:26 AM Go to last post

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