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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Question Clock to 1Ghz with Altera PLL ?

    Started by nono630, February 20th, 2018 01:36 PM
    pll, quartus
    • Replies: 3
    • Views: 153
    Yesterday, 09:34 PM Go to last post
  2. No JTAG after AS programming on EP2C5T144

    Started by Elephantik, February 20th, 2018 02:56 PM
    • Replies: 3
    • Views: 121
    Yesterday, 04:51 PM Go to last post
  3. Cyclone 10 GX supporting DDR3

    Started by ajpatel1987, Yesterday 03:11 PM
    • Replies: 0
    • Views: 44
    Yesterday, 03:11 PM Go to last post
  4. Giving external input to Triple Speed Ethernet

    Started by beginner_EDA, April 3rd, 2014 05:57 AM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 23,188
    Yesterday, 01:04 AM Go to last post
    • Replies: 0
    • Views: 59
    Yesterday, 12:52 AM Go to last post
  5. Export synthesized top-module and import in another project

    Started by dbanks12, February 20th, 2018 10:08 AM
    quartus_pro
    • Replies: 3
    • Views: 102
    February 20th, 2018, 07:22 PM Go to last post
  6. Max10: ADC not working with .pof file

    Started by bienle, February 11th, 2018 11:20 PM
    • Replies: 4
    • Views: 265
    February 19th, 2018, 10:51 PM Go to last post
  7. Config Flash EPCQ4A Cylone II

    Started by MarcFigliuolo, November 6th, 2017 02:56 AM
    • Replies: 6
    • Views: 1,247
    February 19th, 2018, 04:21 PM Go to last post
  8. Max10 NEEK for codec design with external master audio clock?

    Started by BillyZDSP, February 14th, 2018 07:42 PM
    • Replies: 1
    • Views: 180
    February 15th, 2018, 04:45 PM Go to last post
  9. Cyclone IV configuration from 1.8V SoC

    Started by jmce, February 13th, 2018 10:18 AM
    • Replies: 3
    • Views: 285
    February 15th, 2018, 05:38 AM Go to last post
  10. [TCL] query_collection -> why not working?

    Started by dmitryl, January 5th, 2018 04:36 AM
    • Replies: 1
    • Views: 379
    February 14th, 2018, 12:28 PM Go to last post
  11. Unhappy Quartus Prime Lite - Difficulties with simulation

    Started by swinchen, February 6th, 2018 09:22 AM
    • Replies: 9
    • Views: 595
    February 13th, 2018, 05:31 PM Go to last post
    • Replies: 0
    • Views: 209
    February 13th, 2018, 07:59 AM Go to last post
  12. question about Altera Cyclone 2

    Started by booleS, February 13th, 2018 01:31 AM
    • Replies: 1
    • Views: 188
    February 13th, 2018, 04:09 AM Go to last post
  13. Stratix IV security anti tamper fuse

    Started by remi.gauvin, January 30th, 2018 09:56 AM
    anti, fuse, security, tamper
    • Replies: 1
    • Views: 285
    February 12th, 2018, 11:27 PM Go to last post
  14. Terasic DE10 Standard kit and Intel Cyclone V SOC kit

    Started by manhha1402, February 3rd, 2018 03:05 PM
    • Replies: 1
    • Views: 308
    February 12th, 2018, 11:14 PM Go to last post
  15. Problem with SMBUS read stop bit

    Started by steven.mccoy, February 12th, 2018 01:19 PM
    • Replies: 0
    • Views: 164
    February 12th, 2018, 01:19 PM Go to last post
  16. CHANGE_EDREG JTAG instruction via a JAM file

    Started by kb_81, March 21st, 2007 04:14 PM
    • Replies: 4
    • Views: 64,520
    February 12th, 2018, 09:10 AM Go to last post
  17. MAX3000 : Downloading cable

    Started by fabrice, February 12th, 2018 12:03 AM
    max3000 cable
    • Replies: 2
    • Views: 199
    February 12th, 2018, 04:12 AM Go to last post
    • Replies: 2
    • Views: 306
    February 10th, 2018, 03:33 AM Go to last post
  18. Register vs Memory FPGA Cyclone V

    Started by john_altera, February 8th, 2018 09:53 AM
    • Replies: 3
    • Views: 963
    February 9th, 2018, 12:37 PM Go to last post
  19. Cyclone 10 GX EMIF crashes Quartus pro

    Started by mikezgrtf, January 30th, 2018 02:46 PM
    • Replies: 4
    • Views: 358
    February 8th, 2018, 08:28 AM Go to last post
  20. CycloneV FPGA

    Started by Suresh Kumar, February 8th, 2018 02:19 AM
    • Replies: 2
    • Views: 203
    February 8th, 2018, 06:40 AM Go to last post
  21. MAX10 mixed VCCIO for configuration pins

    Started by tnj195, January 16th, 2018 09:32 AM
    • Replies: 2
    • Views: 452
    February 8th, 2018, 04:55 AM Go to last post
  22. Combining pins to source / sink more current

    Started by falconri, February 7th, 2018 07:42 PM
    current, gpio, io pins, sink, source
    • Replies: 2
    • Views: 235
    February 8th, 2018, 02:38 AM Go to last post
  23. Need help with EPM7064BLC44

    Started by Pete16, February 7th, 2018 06:16 PM
    • Replies: 1
    • Views: 194
    February 7th, 2018, 10:05 PM Go to last post
  24. DE1 Board unable to "auto detect" (no hardware)

    Started by Ermanno, January 4th, 2018 02:28 PM
    • Replies: 4
    • Views: 549
    February 7th, 2018, 07:57 PM Go to last post
  25. Problem with MAX 10 pin assignment

    Started by hareesh9415, January 22nd, 2018 03:57 AM
    • Replies: 4
    • Views: 487
    February 7th, 2018, 07:49 PM Go to last post
  26. max10 adc sample point

    Started by qd0090, November 22nd, 2016 02:09 AM
    • Replies: 3
    • Views: 963
    February 7th, 2018, 06:27 PM Go to last post
  27. UART communication problem

    Started by NIDHI PANDA, February 7th, 2018 05:33 AM
    • Replies: 1
    • Views: 205
    February 7th, 2018, 06:57 AM Go to last post

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