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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. FSM POR/Reset State on Cyclone 10 LP

    Started by christnp, Today 06:02 PM
    cyclone 10, fsm, power on reset, power-up level, state
    • Replies: 0
    • Views: 1
    Today, 06:02 PM Go to last post
    • Replies: 1
    • Views: 41
    Today, 01:30 PM Go to last post
  2. Progress FAILED !!! on the programmer.

    Started by ocy, May 18th, 2018 12:29 AM
    • Replies: 4
    • Views: 267
    Today, 04:13 AM Go to last post
  3. migration from EPCQ to EPCQ-A

    Started by tomatoma, May 3rd, 2018 01:54 AM
    • Replies: 9
    • Views: 694
    May 19th, 2018, 11:10 AM Go to last post
  4. Cyclone IV GX transceiver eval board ethernet issue

    Started by bachimanchi, March 30th, 2018 06:02 AM
    • Replies: 1
    • Views: 373
    May 18th, 2018, 06:28 AM Go to last post
  5. PTP 1588 on Cyclone V

    Started by hardwareStudent, July 1st, 2014 11:18 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 19,848
    May 17th, 2018, 10:50 PM Go to last post
    • Replies: 3
    • Views: 319
    May 17th, 2018, 03:11 PM Go to last post
  6. Question Can not program MAX7000

    Started by gwhelbig, May 16th, 2018 02:01 PM
    jtag, max7000, pof, programming
    • Replies: 3
    • Views: 299
    May 17th, 2018, 08:10 AM Go to last post
  7. drive the input pins during the power-up/down sequence

    Started by kstk, May 14th, 2018 08:42 AM
    • Replies: 2
    • Views: 302
    May 15th, 2018, 04:31 AM Go to last post
  8. EPCQ-L Obsolescence

    Started by kstk, May 13th, 2018 12:14 PM
    • Replies: 3
    • Views: 312
    May 14th, 2018, 07:46 PM Go to last post
  9. MSEL driving

    Started by kstk, May 14th, 2018 09:41 AM
    • Replies: 1
    • Views: 235
    May 14th, 2018, 12:10 PM Go to last post
    • Replies: 1
    • Views: 237
    May 14th, 2018, 12:07 PM Go to last post
  10. FPGA Power Measurement

    Started by majdaldin, May 14th, 2018 11:46 AM
    fpga, measurement, power
    • Replies: 0
    • Views: 223
    May 14th, 2018, 11:46 AM Go to last post
  11. EP3C40F780C6 PCIe implementation

    Started by Sathya, May 14th, 2018 08:55 AM
    ep3c40f780c6, pcie
    • Replies: 0
    • Views: 210
    May 14th, 2018, 08:55 AM Go to last post
  12. Standart quartz oscillator

    Started by demsp, May 13th, 2018 11:27 PM
    • Replies: 2
    • Views: 231
    May 14th, 2018, 08:37 AM Go to last post
  13. Don't work DDIO input registers in Arria 10

    Started by andruwkoo, May 14th, 2018 04:21 AM
    altddio, arria10, ddio, ddr input, quartuspro
    • Replies: 0
    • Views: 180
    May 14th, 2018, 04:21 AM Go to last post
  14. Driving Ladder DAC

    Started by Camper, May 8th, 2018 04:14 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 822
    May 13th, 2018, 06:25 AM Go to last post
  15. Erased CFM0 on Max 10 - Can't find JTAG Connection

    Started by smiles, May 10th, 2018 02:53 AM
    cfm, erase, flash, max10, ufm
    • Replies: 2
    • Views: 280
    May 10th, 2018, 09:42 PM Go to last post
    • Replies: 1
    • Views: 274
    May 8th, 2018, 06:42 AM Go to last post
    • Replies: 4
    • Views: 421
    May 8th, 2018, 01:00 AM Go to last post
  16. Question Setting up PCIe Connection Cyclone V

    Started by milleral, April 12th, 2018 02:23 PM
    cyclone v, fpga, pcie
    • Replies: 5
    • Views: 685
    May 6th, 2018, 08:06 AM Go to last post
  17. MEN F210, Cyclone II and Linux

    Started by cifvts, May 4th, 2018 01:38 AM
    • Replies: 0
    • Views: 266
    May 4th, 2018, 01:38 AM Go to last post
  18. DE1 SoC board USB port

    Started by fatimaharr, May 2nd, 2018 01:03 AM
    de1soc, usb
    • Replies: 1
    • Views: 332
    May 3rd, 2018, 07:24 PM Go to last post
  19. Transceiver Rate Match FIFO - Why is it needed?

    Started by DRC, October 16th, 2012 02:53 PM
    • Replies: 6
    • Views: 36,696
    May 3rd, 2018, 11:50 AM Go to last post
  20. Question Stratix II cannot config with JTAG or AS

    Started by qdavid64, May 1st, 2018 05:30 AM
    config_done, ep2s60, stratix ii
    • Replies: 3
    • Views: 372
    May 3rd, 2018, 07:30 AM Go to last post
  21. switching VCCIO Max5 during operation CPLD

    Started by keln, April 27th, 2018 07:44 AM
    • Replies: 1
    • Views: 350
    May 2nd, 2018, 07:42 PM Go to last post
  22. Timequest constraints for a dynamically phase-shifted PLL

    Started by eh291, April 13th, 2018 03:20 PM
    4 Pages
    1 2 3 ... 4
    • Replies: 30
    • Views: 1,892
    May 2nd, 2018, 10:14 AM Go to last post
  23. Usb blaster ii or usb blaster rcn

    Started by ocy, April 26th, 2018 12:11 AM
    • Replies: 3
    • Views: 462
    May 1st, 2018, 09:19 PM Go to last post
  24. Cyclone V bit reversal on Tx PMA

    Started by jrrguzman, May 1st, 2018 04:26 AM
    jesd204b, pma, transceiver
    • Replies: 0
    • Views: 279
    May 1st, 2018, 04:26 AM Go to last post
  25. CPLD max7000 reading

    Started by johntba, April 28th, 2018 08:51 PM
    • Replies: 1
    • Views: 318
    April 30th, 2018, 11:49 PM Go to last post

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