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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. true dual port == 2 x M20Ks

    Started by systom, Yesterday 08:08 PM
    • Replies: 3
    • Views: 48
    Today, 01:16 AM Go to last post
  2. Stratix 10 timing analysis

    Started by AndyN, Yesterday 03:30 PM
    stratix, timequest
    • Replies: 0
    • Views: 43
    Yesterday, 03:30 PM Go to last post
  3. Timequest constraints for a dynamically phase-shifted PLL

    Started by eh291, April 13th, 2018 03:20 PM
    phase-shift, pll, timequest
    • Replies: 3
    • Views: 264
    Yesterday, 07:24 AM Go to last post
  4. Hot-Socketing Arria10 transceiver GX

    Started by kstk, April 17th, 2018 02:21 AM
    • Replies: 2
    • Views: 136
    Yesterday, 03:41 AM Go to last post
  5. MAX10 ADC TSD offset - IO bank 8 voltage?

    Started by tnj195, April 18th, 2018 07:19 AM
    adc, max10, tsd
    • Replies: 1
    • Views: 108
    April 18th, 2018, 07:28 PM Go to last post
  6. FPGA floorplan diagrams

    Started by lefty, April 17th, 2018 08:31 AM
    • Replies: 2
    • Views: 115
    April 17th, 2018, 10:17 AM Go to last post
  7. Export to MOS netlist?

    Started by greglang, April 17th, 2018 03:11 AM
    • Replies: 0
    • Views: 96
    April 17th, 2018, 03:11 AM Go to last post
  8. Max v cpld programming

    Started by harry_blues, April 10th, 2018 09:44 PM
    #cpld, #maxv, #programming, #remote
    • Replies: 1
    • Views: 195
    April 16th, 2018, 10:36 PM Go to last post
    • Replies: 2
    • Views: 258
    April 16th, 2018, 01:13 AM Go to last post
  9. Cyclone IV E, transferring data using serial port

    Started by lukkio, April 1st, 2018 08:55 AM
    2 Pages
    1 2
    • Replies: 18
    • Views: 778
    April 15th, 2018, 03:19 PM Go to last post
  10. In Max II CPLD what is the content of UFM on power up?

    Started by chenbrlv, April 15th, 2018 12:22 AM
    cpld, max ii, ufm
    • Replies: 1
    • Views: 140
    April 15th, 2018, 02:14 AM Go to last post
  11. MAX 10 vs MAX II dynamic power consumption

    Started by Nownuri, April 14th, 2018 08:25 AM
    power
    • Replies: 0
    • Views: 147
    April 14th, 2018, 08:36 AM Go to last post
  12. Implicit MUX selector not drawn?

    Started by greglang, April 14th, 2018 07:17 AM
    • Replies: 1
    • Views: 134
    April 14th, 2018, 08:26 AM Go to last post
  13. Triple Speed Ethernet using DE2-115

    Started by elvissangwa, March 26th, 2018 02:08 PM
    • Replies: 3
    • Views: 408
    April 12th, 2018, 10:10 PM Go to last post
    • Replies: 0
    • Views: 128
    April 12th, 2018, 04:15 PM Go to last post
  14. Question Setting up PCIe Connection Cyclone V

    Started by milleral, April 12th, 2018 02:23 PM
    cyclone v, fpga, pcie
    • Replies: 0
    • Views: 154
    April 12th, 2018, 02:23 PM Go to last post
  15. EyeQ signal measurements

    Started by elisey, April 12th, 2018 06:27 AM
    • Replies: 0
    • Views: 168
    April 12th, 2018, 06:27 AM Go to last post
  16. Unable to generate/find .elf file in NIOS ?

    Started by Saras015, April 12th, 2018 03:12 AM
    • Replies: 1
    • Views: 170
    April 12th, 2018, 04:33 AM Go to last post
    • Replies: 5
    • Views: 507
    April 11th, 2018, 11:44 PM Go to last post
  17. Max 10 + Quartus Prime Pro Edition

    Started by farzin, April 10th, 2018 12:01 PM
    • Replies: 2
    • Views: 257
    April 11th, 2018, 12:42 AM Go to last post
  18. Program cpld max v using ftdi ft4232

    Started by priyal, April 9th, 2018 09:54 PM
    #cpld, #ftdi, #programming, #usbblaster
    • Replies: 5
    • Views: 290
    April 10th, 2018, 09:13 PM Go to last post
  19. CPLD programming using embedded microprocessor

    Started by priyal, April 10th, 2018 01:21 AM
    #cpld, #jtag, #maxv, #programming
    • Replies: 1
    • Views: 189
    April 10th, 2018, 09:54 AM Go to last post
  20. Jam stapl player

    Started by harry_blues, April 10th, 2018 02:18 AM
    #cpld, #jam, #maxv, #programming, #stapl
    • Replies: 1
    • Views: 189
    April 10th, 2018, 03:59 AM Go to last post
    • Replies: 1
    • Views: 231
    April 6th, 2018, 07:14 PM Go to last post
  21. Question Hello World with Cyclone V Development Kit

    Started by milleral, April 6th, 2018 01:31 PM
    .sof, cyclone v, fpga, hello world
    • Replies: 1
    • Views: 222
    April 6th, 2018, 03:50 PM Go to last post
  22. Multiple CPLD's + JTAG's question

    Started by gironja, March 13th, 2018 05:10 AM
    • Replies: 6
    • Views: 476
    April 6th, 2018, 05:47 AM Go to last post
    • Replies: 1
    • Views: 267
    April 5th, 2018, 10:08 AM Go to last post
  23. MAX10 and Flash Update module

    Started by john7, April 2nd, 2018 09:49 PM
    • Replies: 6
    • Views: 443
    April 5th, 2018, 09:44 AM Go to last post
  24. Cyclone 10: definition of "POR time"

    Started by Oscar2, April 3rd, 2018 06:21 AM
    • Replies: 4
    • Views: 384
    April 4th, 2018, 06:34 AM Go to last post
    • Replies: 0
    • Views: 230
    April 4th, 2018, 02:25 AM Go to last post

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