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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 0
    • Views: 32
    Today, 07:12 AM Go to last post
  1. FPGA to SFP

    Started by kharthik, August 10th, 2017 11:04 PM
    • Replies: 7
    • Views: 271
    Today, 06:47 AM Go to last post
    • Replies: 3
    • Views: 57
    Today, 06:16 AM Go to last post
  2. Question Timing parameters of USB Blaster 1

    Started by droe, August 14th, 2017 01:36 AM
    arria10, jtag, timing, usb blaster
    • Replies: 6
    • Views: 164
    Today, 03:05 AM Go to last post
  3. Connecting a PCIe board to a PC

    Started by shaiko, Today 01:37 AM
    • Replies: 1
    • Views: 56
    Today, 02:52 AM Go to last post
  4. Question Looking for FPGA freelancer

    Started by testex, August 14th, 2017 04:57 AM
    contactor, contract, freelance, freelancer
    • Replies: 2
    • Views: 146
    Yesterday, 11:46 PM Go to last post
  5. MAX 10 fails to run JTAG loaded SOF

    Started by jshamlet, August 1st, 2017 06:52 AM
    • Replies: 3
    • Views: 286
    Yesterday, 03:53 AM Go to last post
    • Replies: 0
    • Views: 57
    Yesterday, 03:46 AM Go to last post
  6. MAX 10 in place of Cyclone IV

    Started by Lurkers, August 8th, 2017 07:44 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 430
    August 14th, 2017, 04:07 PM Go to last post
  7. Cyclone V input slew rate

    Started by rozsatib, August 13th, 2017 10:16 AM
    • Replies: 0
    • Views: 88
    August 13th, 2017, 10:16 AM Go to last post
  8. Flex 10k LPM_ADD_SUB issue

    Started by Mux, August 12th, 2017 08:07 PM
    9.2, epf10k10, lpm_add_sub
    • Replies: 1
    • Views: 106
    August 12th, 2017, 10:14 PM Go to last post
  9. 48Mhz XTAL or 12MHz thru PLL x4?

    Started by Lurkers, August 11th, 2017 02:29 PM
    • Replies: 4
    • Views: 209
    August 12th, 2017, 07:47 PM Go to last post
  10. JTAG Boundary Scan Register order for unpackaged device

    Started by ejstrates, August 10th, 2017 10:45 AM
    • Replies: 1
    • Views: 175
    August 11th, 2017, 06:15 AM Go to last post
  11. Question Remote System Update with Max 10 10M16

    Started by KonradH, January 19th, 2017 11:26 PM
    dualconfiguration, max10, qsys, rsu
    • Replies: 8
    • Views: 1,318
    August 11th, 2017, 04:50 AM Go to last post
  12. about MAX V ALTUFM Parallel Interface Timing Spec

    Started by olkhram, August 10th, 2017 02:16 AM
    • Replies: 0
    • Views: 128
    August 10th, 2017, 02:16 AM Go to last post
  13. MAX10 10M50SA power supply requirement for analog feature

    Started by sieg70, August 8th, 2017 02:28 AM
    • Replies: 1
    • Views: 215
    August 9th, 2017, 06:58 AM Go to last post
  14. 10M08SAE144 PCB package drawing question

    Started by technobob, August 8th, 2017 10:11 AM
    • Replies: 1
    • Views: 200
    August 9th, 2017, 06:11 AM Go to last post
  15. Cyclone V ALTLVDS_RX clocking

    Started by karlovic, August 8th, 2017 01:10 AM
    altlvds, cyclone v, fpll, lvds, pll
    • Replies: 0
    • Views: 166
    August 8th, 2017, 01:10 AM Go to last post
  16. Designing a SPI slave

    Started by Lurkers, July 31st, 2017 04:31 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 795
    August 7th, 2017, 04:37 AM Go to last post
  17. does MAX10 10M50SA support CFM UFM and RSU?

    Started by sieg70, July 31st, 2017 02:41 AM
    • Replies: 2
    • Views: 299
    August 7th, 2017, 02:53 AM Go to last post
  18. PLL and ADC in Max 10

    Started by regev91, August 1st, 2017 10:12 PM
    • Replies: 1
    • Views: 235
    August 7th, 2017, 12:19 AM Go to last post
  19. Lightbulb max10 clock

    Started by yadhukr2210, August 3rd, 2017 03:38 AM
    clocking, max10
    • Replies: 1
    • Views: 243
    August 7th, 2017, 12:11 AM Go to last post
    • Replies: 1
    • Views: 637
    August 4th, 2017, 12:34 AM Go to last post
    • Replies: 1
    • Views: 218
    August 3rd, 2017, 08:05 PM Go to last post
  20. Unable to run different versions of altera libraires

    Started by Kalusu, March 20th, 2017 04:56 AM
    • Replies: 3
    • Views: 1,062
    August 3rd, 2017, 07:59 PM Go to last post
    • Replies: 1
    • Views: 203
    August 2nd, 2017, 03:24 AM Go to last post
  21. Arria 10 IBIS zip file from here is not extarcted

    Started by of1234, August 1st, 2017 11:26 PM
    • Replies: 0
    • Views: 148
    August 1st, 2017, 11:26 PM Go to last post
  22. Pin location is too close to PLL clock input pin

    Started by RiccardoRuf, July 25th, 2017 05:03 AM
    • Replies: 2
    • Views: 319
    August 1st, 2017, 07:07 AM Go to last post
  23. How do access the converted MAX 10 ADC results?

    Started by MxBln, January 31st, 2017 04:26 AM
    • Replies: 6
    • Views: 999
    July 30th, 2017, 12:34 PM Go to last post
  24. Question clock problem on De0 nano board (schematics file)

    Started by Irian, July 25th, 2017 04:49 PM
    • Replies: 4
    • Views: 553
    July 28th, 2017, 01:05 PM Go to last post

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