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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Data Transfer from FPGA-to-HPS

    Started by andrew44, June 12th, 2018 11:54 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 511
    Today, 09:37 AM Go to last post
    • Replies: 7
    • Views: 293
    Today, 06:05 AM Go to last post
  2. Interface SD Card through GPIO on DE0-Nano

    Started by macoskey, June 15th, 2018 12:24 PM
    cyclone iv, de0-nano, raspberry pi, sd card
    • Replies: 3
    • Views: 199
    Today, 05:01 AM Go to last post
    • Replies: 1
    • Views: 107
    Today, 04:01 AM Go to last post
  3. EPCS4SI8N bonding diagram

    Started by smithhk, Today 01:19 AM
    • Replies: 0
    • Views: 54
    Today, 01:19 AM Go to last post
  4. nStatus held low Cyclone IV EP4CE6E22

    Started by Labo_elec, Yesterday 12:24 AM
    • Replies: 2
    • Views: 150
    Today, 12:03 AM Go to last post
  5. About path delay in my FPGA

    Started by pan307398668, Yesterday 07:38 PM
    path delay
    • Replies: 0
    • Views: 82
    Yesterday, 07:38 PM Go to last post
  6. Problem with Max 10 I've never seen before

    Started by ddavidd, Yesterday 03:37 PM
    • Replies: 1
    • Views: 96
    Yesterday, 05:22 PM Go to last post
  7. How to design ALM for Aria 10?

    Started by g_tushar, Yesterday 04:26 PM
    alm, multiplexer, verilog
    • Replies: 0
    • Views: 101
    Yesterday, 04:26 PM Go to last post
  8. Cyclone IV EP4CE10E22 circuit examples

    Started by clros, June 17th, 2018 04:55 AM
    • Replies: 1
    • Views: 162
    Yesterday, 09:13 AM Go to last post
  9. max10 - external reset

    Started by Mux, June 17th, 2018 09:39 PM
    max10 reset
    • Replies: 0
    • Views: 102
    June 17th, 2018, 09:39 PM Go to last post
  10. Implementing a Large RAM on Cyclone II - is it possible?

    Started by dan11, June 16th, 2018 01:07 PM
    cyclone ii; ram
    • Replies: 4
    • Views: 199
    June 17th, 2018, 02:03 PM Go to last post
  11. Cyclone IV FPGA (EP4CE10E22) circuit

    Started by clros, June 17th, 2018 05:17 AM
    • Replies: 0
    • Views: 168
    June 17th, 2018, 05:17 AM Go to last post
  12. Max10 Jtag pins as Differential I/O.

    Started by Kozha, June 10th, 2018 12:36 AM
    • Replies: 4
    • Views: 363
    June 17th, 2018, 04:46 AM Go to last post
  13. 5AGXFB3H4F35C5NES device support

    Started by PonyoWoo, June 15th, 2018 08:53 AM
    arria v, arria v gx, arria v gx starter kit, device support
    • Replies: 1
    • Views: 165
    June 16th, 2018, 06:09 PM Go to last post
  14. Spectrum analyzer

    Started by espanyola, June 16th, 2018 05:42 AM
    • Replies: 0
    • Views: 130
    June 16th, 2018, 05:42 AM Go to last post
    • Replies: 1
    • Views: 190
    June 15th, 2018, 06:44 AM Go to last post
  15. Max v cpld programming

    Started by harry_blues, April 10th, 2018 09:44 PM
    #cpld, #maxv, #programming, #remote
    • Replies: 3
    • Views: 1,644
    June 14th, 2018, 07:14 AM Go to last post
  16. MAX-10 FPGA, Voltage level on PLL_CLKOUT pins

    Started by Vadim_GMI, June 14th, 2018 12:41 AM
    i/o, max10, pll, voltage level
    • Replies: 2
    • Views: 179
    June 14th, 2018, 03:27 AM Go to last post
  17. Question MAX-10: IP core for UFM

    Started by SMS, June 10th, 2018 11:50 PM
    • Replies: 9
    • Views: 376
    June 13th, 2018, 10:30 PM Go to last post
  18. Can I configure Cyclone V GT from Parallel Flash?

    Started by shy@navatek.com, June 13th, 2018 08:46 PM
    • Replies: 0
    • Views: 138
    June 13th, 2018, 08:46 PM Go to last post
  19. Timing failure on internal paths

    Started by mohsinele83, June 8th, 2018 03:12 AM
    • Replies: 4
    • Views: 334
    June 13th, 2018, 03:01 AM Go to last post
  20. Strange PLL Clock causing me failing paths in cyc V design

    Started by Hendrik2k1, June 4th, 2018 04:32 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 747
    June 13th, 2018, 02:46 AM Go to last post
    • Replies: 0
    • Views: 156
    June 13th, 2018, 02:04 AM Go to last post
  21. CYCLONE10GX SERDES clock

    Started by lichjr, June 13th, 2018 12:40 AM
    cyclone10gx, serdes
    • Replies: 0
    • Views: 158
    June 13th, 2018, 12:40 AM Go to last post
  22. Fpga alarm clock (urgent help)!

    Started by emrekayar, June 12th, 2018 06:59 AM
    • Replies: 1
    • Views: 154
    June 12th, 2018, 11:31 PM Go to last post
  23. Exclamation Help me my board doesn't work

    Started by daffenen, June 10th, 2018 04:03 AM
    • Replies: 6
    • Views: 363
    June 11th, 2018, 10:28 PM Go to last post
  24. Max10 PLL input clock switchover example?

    Started by bienle, June 11th, 2018 09:56 PM
    • Replies: 0
    • Views: 195
    June 11th, 2018, 09:56 PM Go to last post
  25. DE2-115 board with DCC AD/DA daughter card

    Started by FMZ, June 10th, 2018 01:51 PM
    ad/da card, de2-115
    • Replies: 2
    • Views: 255
    June 11th, 2018, 09:37 PM Go to last post
    • Replies: 4
    • Views: 297
    June 11th, 2018, 08:04 PM Go to last post

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