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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Driving DCLK pin after FPGA configuration

    Started by raja1, Today 05:58 AM
    • Replies: 0
    • Views: 28
    Today, 05:58 AM Go to last post
  2. Using Cypress FX3 as device for Passive Serial

    Started by RickyThomson, December 4th, 2017 02:44 AM
    • Replies: 7
    • Views: 384
    Today, 12:08 AM Go to last post
  3. Looking for 125C Automotive EPCS or EPCQ (replacement) version

    Started by edgar85, October 30th, 2017 06:34 AM
    • Replies: 2
    • Views: 477
    Yesterday, 09:48 AM Go to last post
  4. Please help with PLL

    Started by skliarovartem, Yesterday 04:28 AM
    • Replies: 3
    • Views: 129
    Yesterday, 09:25 AM Go to last post
  5. Arria 10: Packing 2 Multipliers per DSP

    Started by systom, December 12th, 2017 11:44 AM
    arria, dsp, integer, multiplier
    • Replies: 2
    • Views: 142
    December 12th, 2017, 12:03 PM Go to last post
  6. Cyclone V: How to access AS EPCS if booted from HPS?

    Started by Sorgelig, December 12th, 2017 04:09 AM
    • Replies: 1
    • Views: 143
    December 12th, 2017, 07:37 AM Go to last post
  7. Arria 10 multiplier speed

    Started by eazycnc, December 11th, 2017 12:24 AM
    • Replies: 6
    • Views: 219
    December 12th, 2017, 07:05 AM Go to last post
  8. MAX 10 Modular ADC core problem with reserved pins

    Started by ilynxy, December 11th, 2017 03:31 AM
    • Replies: 2
    • Views: 218
    December 11th, 2017, 11:28 PM Go to last post
  9. Help with cyclone iv (ep4ce6e22c8n)

    Started by kurof, December 11th, 2017 03:10 PM
    • Replies: 3
    • Views: 188
    December 11th, 2017, 09:13 PM Go to last post
    • Replies: 3
    • Views: 285
    December 11th, 2017, 07:48 PM Go to last post
  10. How to stream video (and process) into FPGA

    Started by dman, November 21st, 2017 03:08 AM
    2 Pages
    1 2
    camera, ddr, fpga, image, image processing
    • Replies: 15
    • Views: 1,209
    December 11th, 2017, 10:02 AM Go to last post
  11. Cyclone 10 LP Clock input and data in different banks

    Started by Shareef, December 8th, 2017 08:27 AM
    cyclone 10 lp; clock
    • Replies: 1
    • Views: 259
    December 11th, 2017, 05:02 AM Go to last post
  12. Arria V tranceiver clocking

    Started by alcotel, December 7th, 2017 02:05 AM
    • Replies: 2
    • Views: 308
    December 10th, 2017, 02:28 AM Go to last post
  13. Question ALTDDIO_OUT for clock output of chip

    Started by Hendrik2k1, December 6th, 2017 06:26 AM
    • Replies: 7
    • Views: 443
    December 9th, 2017, 05:48 AM Go to last post
  14. [VHDL] Compilation Order

    Started by dmitryl, December 7th, 2017 05:27 PM
    • Replies: 8
    • Views: 431
    December 8th, 2017, 08:01 AM Go to last post
  15. JTAG timing constraints

    Started by daniel@3t.nl, September 25th, 2017 03:48 AM
    2 Pages
    1 2
    • Replies: 17
    • Views: 1,408
    December 7th, 2017, 02:18 PM Go to last post
  16. MAX 10 FPGA Program File

    Started by shevagol777, December 5th, 2017 04:54 AM
    • Replies: 7
    • Views: 457
    December 7th, 2017, 06:12 AM Go to last post
  17. Cyclone 5 mismatch between VCCPD and VCCIO

    Started by sherif123456, December 5th, 2017 03:47 AM
    • Replies: 6
    • Views: 401
    December 6th, 2017, 09:48 PM Go to last post
  18. MAX 10 - Storing configuration in its internal FLASH

    Started by Lurkers, November 23rd, 2017 03:29 PM
    • Replies: 3
    • Views: 386
    December 6th, 2017, 05:59 PM Go to last post
  19. EP20K300EFC672-2X EOl

    Started by dheinz, November 30th, 2017 09:21 AM
    fpga, nsn, obsolete, replacement
    • Replies: 1
    • Views: 288
    December 6th, 2017, 04:18 PM Go to last post
  20. Cyclone IV IBIS Model

    Started by nicx82, December 5th, 2017 12:12 AM
    • Replies: 1
    • Views: 252
    December 5th, 2017, 06:54 PM Go to last post
  21. MAX 10 FPGA power-on/configuration error

    Started by plewis, July 5th, 2017 05:18 AM
    configuration, fpga, max10
    • Replies: 6
    • Views: 1,417
    December 5th, 2017, 05:25 PM Go to last post
  22. Cyclone V PLL : "Normal" mode compensation is not working.

    Started by lundril, December 5th, 2017 09:11 AM
    • Replies: 0
    • Views: 192
    December 5th, 2017, 09:11 AM Go to last post
  23. interfacing to epcq256 through fpga

    Started by alexander14, November 20th, 2017 10:53 AM
    • Replies: 9
    • Views: 824
    December 5th, 2017, 09:03 AM Go to last post
  24. EPCS4SI8N > EPCQ4ASI8N For Old Cyclone FPGA

    Started by mflorczak, December 4th, 2017 08:41 AM
    • Replies: 3
    • Views: 292
    December 5th, 2017, 08:17 AM Go to last post
  25. MAX 10, using LVDS differential clock input.

    Started by emotal, December 4th, 2017 01:17 PM
    • Replies: 2
    • Views: 289
    December 5th, 2017, 08:16 AM Go to last post
  26. Question Interfacing to epcs64 from fpga

    Started by dpenev, December 3rd, 2017 07:37 AM
    epcs64
    • Replies: 7
    • Views: 346
    December 5th, 2017, 07:20 AM Go to last post
  27. Unable to simulate MAX 10 ADC

    Started by RobS, June 15th, 2017 05:03 AM
    adc
    • Replies: 2
    • Views: 915
    December 5th, 2017, 12:53 AM Go to last post
  28. FPGA Development Board - strange shift operation behavior

    Started by mrlsd, November 26th, 2017 04:09 AM
    2 Pages
    1 2
    fpga verilog
    • Replies: 15
    • Views: 939
    December 1st, 2017, 10:09 AM Go to last post
  29. Are there any tutorial or examples about JAM/STAPL?

    Started by cyuz, December 1st, 2017 05:00 AM
    boundary scan, jam/stapl
    • Replies: 0
    • Views: 229
    December 1st, 2017, 05:00 AM Go to last post

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