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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 5
    • Views: 180
    Today, 11:12 PM Go to last post
  1. max10 - external reset

    Started by Mux, Today 09:39 PM
    max10 reset
    • Replies: 0
    • Views: 14
    Today, 09:39 PM Go to last post
    • Replies: 4
    • Views: 139
    Today, 02:03 PM Go to last post
  2. Cyclone IV FPGA (EP4CE10E22) circuit

    Started by clros, Today 05:17 AM
    • Replies: 0
    • Views: 74
    Today, 05:17 AM Go to last post
  3. Cyclone IV EP4CE10E22 circuit examples

    Started by clros, Today 04:55 AM
    • Replies: 0
    • Views: 64
    Today, 04:55 AM Go to last post
  4. Max10 Jtag pins as Differential I/O.

    Started by Kozha, June 10th, 2018 12:36 AM
    • Replies: 4
    • Views: 320
    Today, 04:46 AM Go to last post
  5. 5AGXFB3H4F35C5NES device support

    Started by PonyoWoo, June 15th, 2018 08:53 AM
    arria v, arria v gx, arria v gx starter kit, device support
    • Replies: 1
    • Views: 123
    Yesterday, 06:09 PM Go to last post
  6. Spectrum analyzer

    Started by espanyola, Yesterday 05:42 AM
    • Replies: 0
    • Views: 90
    Yesterday, 05:42 AM Go to last post
  7. Interface SD Card through GPIO on DE0-Nano

    Started by macoskey, June 15th, 2018 12:24 PM
    cyclone iv, de0-nano, raspberry pi, sd card
    • Replies: 0
    • Views: 115
    June 15th, 2018, 12:24 PM Go to last post
    • Replies: 1
    • Views: 149
    June 15th, 2018, 06:44 AM Go to last post
  8. Max v cpld programming

    Started by harry_blues, April 10th, 2018 09:44 PM
    #cpld, #maxv, #programming, #remote
    • Replies: 3
    • Views: 1,609
    June 14th, 2018, 07:14 AM Go to last post
  9. MAX-10 FPGA, Voltage level on PLL_CLKOUT pins

    Started by Vadim_GMI, June 14th, 2018 12:41 AM
    i/o, max10, pll, voltage level
    • Replies: 2
    • Views: 146
    June 14th, 2018, 03:27 AM Go to last post
  10. Question MAX-10: IP core for UFM

    Started by SMS, June 10th, 2018 11:50 PM
    • Replies: 9
    • Views: 326
    June 13th, 2018, 10:30 PM Go to last post
  11. Can I configure Cyclone V GT from Parallel Flash?

    Started by shy@navatek.com, June 13th, 2018 08:46 PM
    • Replies: 0
    • Views: 112
    June 13th, 2018, 08:46 PM Go to last post
  12. Data Transfer from FPGA-to-HPS

    Started by andrew44, June 12th, 2018 11:54 AM
    cyclonev, de0-nano-soc
    • Replies: 6
    • Views: 345
    June 13th, 2018, 01:21 PM Go to last post
  13. Timing failure on internal paths

    Started by mohsinele83, June 8th, 2018 03:12 AM
    • Replies: 4
    • Views: 301
    June 13th, 2018, 03:01 AM Go to last post
  14. Strange PLL Clock causing me failing paths in cyc V design

    Started by Hendrik2k1, June 4th, 2018 04:32 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 682
    June 13th, 2018, 02:46 AM Go to last post
    • Replies: 0
    • Views: 123
    June 13th, 2018, 02:04 AM Go to last post
  15. CYCLONE10GX SERDES clock

    Started by lichjr, June 13th, 2018 12:40 AM
    cyclone10gx, serdes
    • Replies: 0
    • Views: 125
    June 13th, 2018, 12:40 AM Go to last post
  16. Fpga alarm clock (urgent help)!

    Started by emrekayar, June 12th, 2018 06:59 AM
    • Replies: 1
    • Views: 124
    June 12th, 2018, 11:31 PM Go to last post
  17. Exclamation Help me my board doesn't work

    Started by daffenen, June 10th, 2018 04:03 AM
    • Replies: 6
    • Views: 320
    June 11th, 2018, 10:28 PM Go to last post
  18. Max10 PLL input clock switchover example?

    Started by bienle, June 11th, 2018 09:56 PM
    • Replies: 0
    • Views: 163
    June 11th, 2018, 09:56 PM Go to last post
  19. DE2-115 board with DCC AD/DA daughter card

    Started by FMZ, June 10th, 2018 01:51 PM
    ad/da card, de2-115
    • Replies: 2
    • Views: 220
    June 11th, 2018, 09:37 PM Go to last post
    • Replies: 4
    • Views: 265
    June 11th, 2018, 08:04 PM Go to last post
    • Replies: 2
    • Views: 202
    June 11th, 2018, 06:30 PM Go to last post
    • Replies: 2
    • Views: 231
    June 11th, 2018, 11:52 AM Go to last post
  20. Least painless way to get data in & out of FPGA

    Started by eugenek, June 10th, 2018 12:41 PM
    • Replies: 2
    • Views: 234
    June 11th, 2018, 12:48 AM Go to last post
  21. Post FPGA MAX 10: JTAG secure mode

    Started by jayr, June 7th, 2018 09:27 AM
    encryption, fpga, jtag secure mode, max10
    • Replies: 3
    • Views: 269
    June 10th, 2018, 08:25 PM Go to last post
  22. MAX 10 CFM0 not programed

    Started by jylo, June 9th, 2018 12:51 AM
    • Replies: 2
    • Views: 205
    June 9th, 2018, 07:19 AM Go to last post
  23. altsyncram 1 word

    Started by alteraaditya, June 3rd, 2018 12:49 AM
    • Replies: 3
    • Views: 351
    June 8th, 2018, 05:10 PM Go to last post

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