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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Data Transfer from PC to FPGA

    Started by jaribro, Yesterday 10:48 PM
    • Replies: 0
    • Views: 7
    Yesterday, 10:48 PM Go to last post
    • Replies: 0
    • Views: 17
    Yesterday, 08:12 PM Go to last post
  2. Max10 10M08SAU169 Layout, PDN tool required?

    Started by synchronous, Yesterday 04:16 AM
    de-coupling caps, max10, pcb layout, pdn
    • Replies: 3
    • Views: 74
    Yesterday, 08:03 AM Go to last post
  3. Low cost FPGAs with dual Gigabit Ethernet controller.

    Started by fiedel, July 21st, 2017 07:19 AM
    • Replies: 1
    • Views: 109
    July 21st, 2017, 10:29 AM Go to last post
  4. Multiple Configuration File for Cyclone IV E

    Started by shauk, May 30th, 2017 04:51 AM
    cyclone iv e
    • Replies: 6
    • Views: 736
    July 21st, 2017, 01:06 AM Go to last post
  5. Two kinds of EP4SE530H35I3N

    Started by eRen, July 20th, 2017 08:15 AM
    • Replies: 1
    • Views: 112
    July 20th, 2017, 08:39 AM Go to last post
  6. Max10 10m25 dual supply; jtag volatge

    Started by nicx82, July 19th, 2017 08:21 AM
    • Replies: 1
    • Views: 139
    July 20th, 2017, 01:55 AM Go to last post
  7. PLL is not working in Cylcone V GX (Using Integer PLL)

    Started by kharthik, July 19th, 2017 04:19 AM
    • Replies: 4
    • Views: 169
    July 20th, 2017, 01:38 AM Go to last post
    • Replies: 3
    • Views: 468
    July 20th, 2017, 12:00 AM Go to last post
  8. MAX V CFM write/erase fatigue failure mode

    Started by sonictj, July 19th, 2017 11:49 PM
    • Replies: 0
    • Views: 65
    July 19th, 2017, 11:49 PM Go to last post
  9. how to set values in the same register in the PL side

    Started by Sfato, July 19th, 2017 03:56 AM
    • Replies: 0
    • Views: 104
    July 19th, 2017, 03:56 AM Go to last post
  10. banks sharing VCCPD pins

    Started by rod@ariradesign.com, July 18th, 2017 03:14 PM
    • Replies: 1
    • Views: 144
    July 19th, 2017, 03:05 AM Go to last post
  11. Post UFM verification method (VCS)

    Started by Tadanori_ikeda, July 13th, 2017 09:19 PM
    usm synopsys vcs
    • Replies: 1
    • Views: 244
    July 18th, 2017, 05:01 PM Go to last post
  12. How to disable I/O Bank Source Voltage

    Started by serway, July 18th, 2017 06:57 AM
    • Replies: 2
    • Views: 176
    July 18th, 2017, 11:48 AM Go to last post
  13. SignalTap fails timing often

    Started by rozsatib, July 18th, 2017 06:24 AM
    • Replies: 6
    • Views: 267
    July 18th, 2017, 11:25 AM Go to last post
  14. Design altera FPGA board

    Started by creatives, July 16th, 2017 06:48 AM
    board design, fpga
    • Replies: 4
    • Views: 285
    July 18th, 2017, 06:38 AM Go to last post
  15. MAX10: Altera GPIO Lite

    Started by vlrean, July 18th, 2017 02:57 AM
    • Replies: 0
    • Views: 132
    July 18th, 2017, 02:57 AM Go to last post
    • Replies: 0
    • Views: 155
    July 17th, 2017, 05:54 AM Go to last post
  16. .jic file checksum

    Started by denoise, July 17th, 2017 05:06 AM
    checksum, crc, jic
    • Replies: 0
    • Views: 123
    July 17th, 2017, 05:06 AM Go to last post
  17. MAX10 Remote system Upgrade

    Started by sruthi.1914, July 17th, 2017 03:31 AM
    cpld, max 10 - rsu, max 10- reconfiguration
    • Replies: 0
    • Views: 116
    July 17th, 2017, 03:31 AM Go to last post
  18. MAX10 Dual Configuraion IP

    Started by sruthi.1914, July 17th, 2017 03:13 AM
    cpld, max10 - rsu, remote system upgrade
    • Replies: 0
    • Views: 104
    July 17th, 2017, 03:13 AM Go to last post
  19. There are no Nios II CPUs

    Started by bassem, May 23rd, 2012 08:10 AM
    • Replies: 3
    • Views: 34,544
    July 16th, 2017, 10:39 PM Go to last post
  20. STRATIX10 Configuration time

    Started by GVAISMAN, July 3rd, 2017 11:05 PM
    • Replies: 1
    • Views: 269
    July 16th, 2017, 10:37 PM Go to last post
  21. Cyclone III + EPCS4 + UART remote upgrade

    Started by zhangyi17, July 21st, 2016 06:24 AM
    • Replies: 7
    • Views: 1,294
    July 16th, 2017, 10:31 PM Go to last post
  22. Arria V SoC Development Board

    Started by Selmesal, July 14th, 2017 02:22 PM
    • Replies: 1
    • Views: 243
    July 16th, 2017, 10:22 PM Go to last post
    • Replies: 0
    • Views: 151
    July 16th, 2017, 03:09 AM Go to last post
  23. MAX10 RSU unconstrained clocks

    Started by dbollish, July 12th, 2017 02:04 PM
    • Replies: 4
    • Views: 376
    July 13th, 2017, 01:01 PM Go to last post
  24. Test stratix iv

    Started by nick8989, July 12th, 2017 07:54 AM
    • Replies: 0
    • Views: 183
    July 12th, 2017, 07:54 AM Go to last post
  25. MAX10 Remote System Upgrade- Program Error

    Started by sruthi.1914, July 12th, 2017 01:05 AM
    max10-field upgrade, max10-rsu, onchip flash ip core
    • Replies: 0
    • Views: 221
    July 12th, 2017, 01:05 AM Go to last post
  26. Arria 10 DDR multi-port front end not suported?

    Started by Q..Li, July 11th, 2017 12:00 AM
    • Replies: 2
    • Views: 306
    July 11th, 2017, 10:41 AM Go to last post

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