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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. MAX 10: using two ALTPLL

    Started by emotal, February 23rd, 2018 11:36 AM
    • Replies: 1
    • Views: 94
    Yesterday, 11:27 PM Go to last post
  2. Cyclone 10 LP DDR IO-cell information

    Started by josyb, February 3rd, 2018 05:07 AM
    • Replies: 6
    • Views: 439
    Yesterday, 08:20 AM Go to last post
  3. How to reduced intradomain skew in Alter FPGA!

    Started by superjoe, March 11th, 2013 05:05 PM
    • Replies: 2
    • Views: 26,782
    February 23rd, 2018, 12:24 PM Go to last post
  4. Cyclone IV not detecting on blaster

    Started by abhinipun, February 23rd, 2018 02:08 AM
    cyclone iv, identification, usb, usb blaster
    • Replies: 1
    • Views: 118
    February 23rd, 2018, 04:30 AM Go to last post
  5. EPCQ and EPCQ-L are discontinued (notification 02/14/2018)

    Started by FateS, February 21st, 2018 12:52 AM
    • Replies: 3
    • Views: 523
    February 23rd, 2018, 12:27 AM Go to last post
  6. Export synthesized top-module and import in another project

    Started by dbanks12, February 20th, 2018 10:08 AM
    quartus_pro
    • Replies: 5
    • Views: 207
    February 22nd, 2018, 08:46 AM Go to last post
  7. Missing figure in documentation

    Started by Selmesal, February 22nd, 2018 06:01 AM
    • Replies: 1
    • Views: 118
    February 22nd, 2018, 06:33 AM Go to last post
  8. MAX 10 PCI 3.0V vs 3.3V

    Started by Selmesal, February 22nd, 2018 06:00 AM
    • Replies: 0
    • Views: 107
    February 22nd, 2018, 06:00 AM Go to last post
  9. Question Clock to 1Ghz with Altera PLL ?

    Started by nono630, February 20th, 2018 01:36 PM
    pll, quartus
    • Replies: 3
    • Views: 275
    February 21st, 2018, 09:34 PM Go to last post
  10. No JTAG after AS programming on EP2C5T144

    Started by Elephantik, February 20th, 2018 02:56 PM
    • Replies: 3
    • Views: 218
    February 21st, 2018, 04:51 PM Go to last post
  11. Cyclone 10 GX supporting DDR3

    Started by ajpatel1987, February 21st, 2018 03:11 PM
    • Replies: 0
    • Views: 137
    February 21st, 2018, 03:11 PM Go to last post
  12. Giving external input to Triple Speed Ethernet

    Started by beginner_EDA, April 3rd, 2014 05:57 AM
    3 Pages
    1 2 3
    • Replies: 26
    • Views: 23,271
    February 21st, 2018, 01:04 AM Go to last post
  13. Max10: ADC not working with .pof file

    Started by bienle, February 11th, 2018 11:20 PM
    • Replies: 4
    • Views: 308
    February 19th, 2018, 10:51 PM Go to last post
  14. Config Flash EPCQ4A Cylone II

    Started by MarcFigliuolo, November 6th, 2017 02:56 AM
    • Replies: 6
    • Views: 1,323
    February 19th, 2018, 04:21 PM Go to last post
  15. Max10 NEEK for codec design with external master audio clock?

    Started by BillyZDSP, February 14th, 2018 07:42 PM
    • Replies: 1
    • Views: 208
    February 15th, 2018, 04:45 PM Go to last post
  16. Cyclone IV configuration from 1.8V SoC

    Started by jmce, February 13th, 2018 10:18 AM
    • Replies: 3
    • Views: 311
    February 15th, 2018, 05:38 AM Go to last post
  17. [TCL] query_collection -> why not working?

    Started by dmitryl, January 5th, 2018 04:36 AM
    • Replies: 1
    • Views: 404
    February 14th, 2018, 12:28 PM Go to last post
  18. Unhappy Quartus Prime Lite - Difficulties with simulation

    Started by swinchen, February 6th, 2018 09:22 AM
    • Replies: 9
    • Views: 776
    February 13th, 2018, 05:31 PM Go to last post
    • Replies: 0
    • Views: 245
    February 13th, 2018, 07:59 AM Go to last post
  19. question about Altera Cyclone 2

    Started by booleS, February 13th, 2018 01:31 AM
    • Replies: 1
    • Views: 224
    February 13th, 2018, 04:09 AM Go to last post
  20. Stratix IV security anti tamper fuse

    Started by remi.gauvin, January 30th, 2018 09:56 AM
    anti, fuse, security, tamper
    • Replies: 1
    • Views: 313
    February 12th, 2018, 11:27 PM Go to last post
  21. Terasic DE10 Standard kit and Intel Cyclone V SOC kit

    Started by manhha1402, February 3rd, 2018 03:05 PM
    • Replies: 1
    • Views: 353
    February 12th, 2018, 11:14 PM Go to last post
  22. Problem with SMBUS read stop bit

    Started by steven.mccoy, February 12th, 2018 01:19 PM
    • Replies: 0
    • Views: 196
    February 12th, 2018, 01:19 PM Go to last post
  23. CHANGE_EDREG JTAG instruction via a JAM file

    Started by kb_81, March 21st, 2007 04:14 PM
    • Replies: 4
    • Views: 64,546
    February 12th, 2018, 09:10 AM Go to last post
  24. MAX3000 : Downloading cable

    Started by fabrice, February 12th, 2018 12:03 AM
    max3000 cable
    • Replies: 2
    • Views: 233
    February 12th, 2018, 04:12 AM Go to last post
    • Replies: 2
    • Views: 343
    February 10th, 2018, 03:33 AM Go to last post
  25. Register vs Memory FPGA Cyclone V

    Started by john_altera, February 8th, 2018 09:53 AM
    • Replies: 3
    • Views: 1,029
    February 9th, 2018, 12:37 PM Go to last post
  26. Cyclone 10 GX EMIF crashes Quartus pro

    Started by mikezgrtf, January 30th, 2018 02:46 PM
    • Replies: 4
    • Views: 403
    February 8th, 2018, 08:28 AM Go to last post
  27. CycloneV FPGA

    Started by Suresh Kumar, February 8th, 2018 02:19 AM
    • Replies: 2
    • Views: 232
    February 8th, 2018, 06:40 AM Go to last post
  28. MAX10 mixed VCCIO for configuration pins

    Started by tnj195, January 16th, 2018 09:32 AM
    • Replies: 2
    • Views: 497
    February 8th, 2018, 04:55 AM Go to last post

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