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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Cyclone V E Development Kit failed on Active Serial Configuration via JTAG

    Started by john_altera, November 15th, 2017 09:57 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 607
    Today, 02:00 AM Go to last post
  2. Choosing a FPGA

    Started by Shiromini, Today 01:29 AM
    • Replies: 0
    • Views: 28
    Today, 01:29 AM Go to last post
  3. Storing password input using PS/2 keyboard

    Started by joert45, Yesterday 08:12 PM
    • Replies: 1
    • Views: 45
    Yesterday, 10:33 PM Go to last post
    • Replies: 2
    • Views: 60
    Yesterday, 06:42 PM Go to last post
  4. A question about fitting resource usage summary

    Started by yh4e10, August 18th, 2011 02:16 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 34,164
    Yesterday, 11:16 AM Go to last post
    • Replies: 2
    • Views: 84
    Yesterday, 02:28 AM Go to last post
  5. Mapping block RAMs to specific address space

    Started by engg_sajjad, November 22nd, 2017 03:24 PM
    fpga
    • Replies: 1
    • Views: 88
    November 22nd, 2017, 09:35 PM Go to last post
  6. How to stream video (and process) into FPGA

    Started by dman, November 21st, 2017 03:08 AM
    2 Pages
    1 2
    camera, ddr, fpga, image, image processing
    • Replies: 10
    • Views: 301
    November 22nd, 2017, 08:03 AM Go to last post
  7. MAX10 PLL Not Locking - KHz instead of MHz

    Started by wblee, November 17th, 2017 12:54 AM
    • Replies: 2
    • Views: 191
    November 21st, 2017, 09:09 PM Go to last post
  8. interfacing to epcq from fpga?

    Started by alexander14, November 7th, 2017 12:13 PM
    • Replies: 4
    • Views: 357
    November 21st, 2017, 06:24 AM Go to last post
  9. interfacing to epcq256 through fpga

    Started by alexander14, November 20th, 2017 10:53 AM
    • Replies: 2
    • Views: 150
    November 21st, 2017, 01:28 AM Go to last post
  10. Stuck on Fast QSPI

    Started by skrasms, November 7th, 2017 10:47 PM
    • Replies: 8
    • Views: 623
    November 20th, 2017, 06:12 PM Go to last post
  11. Cyclone V 12bit LVDS deserialisation.

    Started by Boscoe, November 20th, 2017 03:44 AM
    • Replies: 3
    • Views: 170
    November 20th, 2017, 12:45 PM Go to last post
  12. MAX10 constraining IO problems

    Started by cmorley, November 15th, 2017 07:45 AM
    • Replies: 3
    • Views: 225
    November 20th, 2017, 11:26 AM Go to last post
  13. interfacing to epcq256 through fpga

    Started by alexander14, November 20th, 2017 11:06 AM
    • Replies: 0
    • Views: 57
    November 20th, 2017, 11:06 AM Go to last post
  14. Cyclone V won't configure via active serial

    Started by rod@ariradesign.com, November 13th, 2017 02:14 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 570
    November 20th, 2017, 03:41 AM Go to last post
  15. Open Source MAX10 dev board

    Started by cyg, November 18th, 2017 11:20 PM
    • Replies: 0
    • Views: 173
    November 18th, 2017, 11:20 PM Go to last post
  16. Would you recommend "new" Cyclone 10 GX now for a new design??

    Started by FateS, November 16th, 2017 08:38 AM
    • Replies: 2
    • Views: 254
    November 17th, 2017, 09:00 AM Go to last post
  17. DDR II SDRAM Data Mask Pins assignments

    Started by mohsin_qau, November 9th, 2017 05:15 AM
    • Replies: 2
    • Views: 327
    November 17th, 2017, 01:27 AM Go to last post
  18. Unhappy Can't fit fan-out of node into a single clock region

    Started by tiabph, September 4th, 2009 04:46 AM
    • Replies: 2
    • Views: 45,917
    November 16th, 2017, 02:42 AM Go to last post
  19. problem with adaptive FIR ,i realy need your help

    Started by boyzzun, March 3rd, 2014 07:44 AM
    • Replies: 9
    • Views: 19,297
    November 15th, 2017, 12:16 PM Go to last post
  20. MAX 10 and the STAPL byte-code player

    Started by LordNikon, March 2nd, 2017 05:27 AM
    • Replies: 5
    • Views: 1,185
    November 14th, 2017, 04:53 AM Go to last post
  21. Cyclone V Hard Memory Controller MPFE bandwidth

    Started by simonkbrown, November 13th, 2017 04:45 PM
    cyclone, ddr, hmc, mpfe
    • Replies: 0
    • Views: 179
    November 13th, 2017, 04:45 PM Go to last post
  22. MAX10 PLL External Clock Output

    Started by JDL, November 7th, 2017 08:34 AM
    pll max10
    • Replies: 2
    • Views: 330
    November 13th, 2017, 03:55 AM Go to last post
    • Replies: 5
    • Views: 438
    November 13th, 2017, 01:46 AM Go to last post
  23. Product Key MAX 7000

    Started by MarcFigliuolo, November 10th, 2017 07:09 AM
    • Replies: 2
    • Views: 329
    November 12th, 2017, 07:15 PM Go to last post
  24. M20K block related build error

    Started by matttsai, November 4th, 2017 06:05 AM
    • Replies: 2
    • Views: 403
    November 12th, 2017, 07:05 PM Go to last post
  25. MAX 10 10M25SAE144 problem boot from internal flash

    Started by siliconvalley, November 5th, 2017 09:27 AM
    config, max10
    • Replies: 7
    • Views: 581
    November 10th, 2017, 05:34 PM Go to last post
  26. Problem with simulation and implementation of code in DE0 Nano Cyclone IV kit

    Started by abenitez, November 7th, 2017 08:21 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 697
    November 10th, 2017, 11:16 AM Go to last post
  27. MAX10 RAM (M9K) content at power up?

    Started by arg, November 9th, 2017 01:09 PM
    • Replies: 2
    • Views: 333
    November 10th, 2017, 02:01 AM Go to last post

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