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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. ROM Initialization, Max 10 device 10M02

    Started by synchronous, June 17th, 2016 03:15 PM
    10m02, error 16031, max 10
    • Replies: 3
    • Views: 3,116
    July 13th, 2018, 08:10 AM Go to last post
    • Replies: 0
    • Views: 233
    July 12th, 2018, 06:42 AM Go to last post
  2. PCIE to DDR4

    Started by aazz44ss, July 11th, 2018 10:58 PM
    • Replies: 1
    • Views: 161
    July 12th, 2018, 12:05 AM Go to last post
  3. Max II Life cycle

    Started by Oren Bash, July 11th, 2018 11:28 PM
    • Replies: 0
    • Views: 133
    July 11th, 2018, 11:28 PM Go to last post
    • Replies: 0
    • Views: 128
    July 11th, 2018, 11:10 PM Go to last post
  4. Question MAX-10: IP core for UFM

    Started by SMS, June 10th, 2018 11:50 PM
    2 Pages
    1 2
    • Replies: 11
    • Views: 932
    July 11th, 2018, 08:12 PM Go to last post
  5. Question Can I expect PLL outputs to be in phase?

    Started by xflatx, July 11th, 2018 10:10 AM
    • Replies: 2
    • Views: 181
    July 11th, 2018, 02:41 PM Go to last post
  6. Unhappy Cannot connect PLL to internal signal in Cyclone IV

    Started by cosmin, July 8th, 2018 02:34 PM
    cyclone, pll
    • Replies: 2
    • Views: 243
    July 10th, 2018, 05:09 PM Go to last post
    • Replies: 3
    • Views: 201
    July 10th, 2018, 01:50 AM Go to last post
  7. Red face MAX7000A's JTAG instruction

    Started by zhangwenhe, July 9th, 2018 04:11 AM
    instruction, jtag, max7000a, mcu, program
    • Replies: 1
    • Views: 170
    July 9th, 2018, 08:15 PM Go to last post
  8. MAX 10 ordering "VB"

    Started by vader555, July 9th, 2018 12:28 PM
    max 10
    • Replies: 1
    • Views: 152
    July 9th, 2018, 04:18 PM Go to last post
  9. MAX10 - Remote reconfiguration

    Started by jgiampiccolo, August 9th, 2015 11:58 PM
    • Replies: 8
    • Views: 4,242
    July 9th, 2018, 10:00 AM Go to last post
  10. cyclon does not load

    Started by progsel, July 8th, 2018 12:08 PM
    • Replies: 6
    • Views: 275
    July 9th, 2018, 08:22 AM Go to last post
  11. Looking for a configuration manual for Cyclone V SoC

    Started by Pavel_47, July 6th, 2018 02:40 AM
    • Replies: 1
    • Views: 200
    July 9th, 2018, 05:09 AM Go to last post
  12. Cyclone V E Uniphy Controller Error 174077

    Started by tmny277, July 5th, 2018 12:01 PM
    • Replies: 2
    • Views: 243
    July 6th, 2018, 04:53 AM Go to last post
  13. Importance of set_input_delay

    Started by PeterB, July 5th, 2018 10:54 PM
    • Replies: 0
    • Views: 186
    July 5th, 2018, 10:54 PM Go to last post
  14. VHDL Port Mismatch Error

    Started by RSK007, June 29th, 2018 07:54 AM
    • Replies: 6
    • Views: 440
    July 5th, 2018, 01:01 PM Go to last post
  15. Cyclone V Uniphy controller fitter error 174077

    Started by tmny277, July 5th, 2018 11:41 AM
    • Replies: 0
    • Views: 195
    July 5th, 2018, 11:41 AM Go to last post
  16. Timing closure

    Started by C1Ron, July 5th, 2018 03:26 AM
    • Replies: 3
    • Views: 267
    July 5th, 2018, 09:09 AM Go to last post
  17. Replacing EPCS128 with EPCQ128A configuration memory

    Started by JoakimW, July 2nd, 2018 07:51 AM
    configuration memory, epcq, epcq128a, epcs, epcs128
    • Replies: 1
    • Views: 242
    July 5th, 2018, 01:23 AM Go to last post
    • Replies: 0
    • Views: 176
    July 5th, 2018, 12:31 AM Go to last post
    • Replies: 1
    • Views: 231
    July 5th, 2018, 12:15 AM Go to last post
    • Replies: 3
    • Views: 322
    July 5th, 2018, 12:12 AM Go to last post
    • Replies: 4
    • Views: 303
    July 4th, 2018, 11:44 PM Go to last post
  18. MAX10: USB Blaster uploads to flash or SRAM?

    Started by Sorgelig, July 4th, 2018 06:31 AM
    • Replies: 1
    • Views: 278
    July 4th, 2018, 05:57 PM Go to last post
  19. Hex file different widths Maxplus II and Quartus 9.0

    Started by Relay Man, July 4th, 2018 03:04 AM
    • Replies: 0
    • Views: 180
    July 4th, 2018, 03:04 AM Go to last post
  20. FS2 support for Cyclone 5 FPGAs

    Started by user2018, July 2nd, 2018 08:54 AM
    • Replies: 1
    • Views: 278
    July 3rd, 2018, 07:42 AM Go to last post
  21. Using Timequest to Analyze Processor Bus Interface

    Started by OG_973, June 21st, 2018 10:20 AM
    bus, processor, timequest
    • Replies: 7
    • Views: 686
    July 3rd, 2018, 12:21 AM Go to last post
  22. Question Cyclone IV PLL Reconfiguration parameter setting

    Started by brotherzhao, July 2nd, 2018 12:20 AM
    cyclone iv, pll, reconfiguration
    • Replies: 2
    • Views: 227
    July 2nd, 2018, 06:04 AM Go to last post
    • Replies: 3
    • Views: 404
    July 2nd, 2018, 12:20 AM Go to last post

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