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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Post PCI Express Root port with a Nios II

    Started by remhi.ch, Today 05:45 AM
    arria, express, pci, port, root
    • Replies: 0
    • Views: 26
    Today, 05:45 AM Go to last post
  2. Timequest constraints for a dynamically phase-shifted PLL

    Started by eh291, April 13th, 2018 03:20 PM
    2 Pages
    1 2
    • Replies: 12
    • Views: 589
    Today, 12:26 AM Go to last post
  3. Usb blaster ii or usb blaster rcn

    Started by ocy, Today 12:11 AM
    • Replies: 0
    • Views: 64
    Today, 12:11 AM Go to last post
  4. 10779 VHDL ERROR : expression is not constant

    Started by ocy, April 24th, 2018 05:02 AM
    • Replies: 6
    • Views: 175
    Yesterday, 11:03 PM Go to last post
  5. Cyclone IV Speed Grade and Fmax Relationship

    Started by shauk, Yesterday 02:43 AM
    • Replies: 1
    • Views: 87
    Yesterday, 09:58 PM Go to last post
  6. MAX10 and Flash Update module

    Started by john7, April 2nd, 2018 09:49 PM
    2 Pages
    1 2
    • Replies: 14
    • Views: 690
    Yesterday, 10:16 AM Go to last post
  7. Unused Bank VCCIO for Arria 10

    Started by kstk, April 24th, 2018 03:21 AM
    • Replies: 2
    • Views: 140
    Yesterday, 04:00 AM Go to last post
    • Replies: 5
    • Views: 182
    Yesterday, 03:17 AM Go to last post
    • Replies: 3
    • Views: 226
    Yesterday, 01:54 AM Go to last post
    • Replies: 2
    • Views: 185
    April 24th, 2018, 06:19 PM Go to last post
  8. true dual port == 2 x M20Ks

    Started by systom, April 19th, 2018 08:08 PM
    • Replies: 9
    • Views: 289
    April 23rd, 2018, 12:34 PM Go to last post
  9. Hot-Socketing Arria10 transceiver GX

    Started by kstk, April 17th, 2018 02:21 AM
    • Replies: 3
    • Views: 229
    April 23rd, 2018, 07:55 AM Go to last post
  10. SPI ram and Nios on FPGA MAX10

    Started by perryiavo, October 20th, 2017 01:59 AM
    max10, nios, ram, spi, spi ram
    • Replies: 5
    • Views: 1,479
    April 23rd, 2018, 07:12 AM Go to last post
    • Replies: 5
    • Views: 219
    April 23rd, 2018, 03:35 AM Go to last post
  11. Multiple connections to USB Blaster

    Started by uivil, April 20th, 2018 08:55 PM
    connections, cycloneii, signal tap, usb blaster
    • Replies: 3
    • Views: 205
    April 21st, 2018, 07:05 PM Go to last post
  12. Using NIOS with CvP

    Started by bzuiss, April 20th, 2018 09:27 AM
    • Replies: 0
    • Views: 145
    April 20th, 2018, 09:27 AM Go to last post
  13. FPGA Project_ Altera Cyclone IV EP4CE6E22C8N

    Started by thanhphuc95, April 20th, 2018 07:24 AM
    • Replies: 0
    • Views: 61
    April 20th, 2018, 07:24 AM Go to last post
  14. Stratix 10 timing analysis

    Started by AndyN, April 19th, 2018 03:30 PM
    stratix, timequest
    • Replies: 0
    • Views: 138
    April 19th, 2018, 03:30 PM Go to last post
  15. MAX10 ADC TSD offset - IO bank 8 voltage?

    Started by tnj195, April 18th, 2018 07:19 AM
    adc, max10, tsd
    • Replies: 2
    • Views: 160
    April 19th, 2018, 12:26 AM Go to last post
  16. FPGA floorplan diagrams

    Started by lefty, April 17th, 2018 08:31 AM
    • Replies: 2
    • Views: 165
    April 17th, 2018, 10:17 AM Go to last post
  17. Export to MOS netlist?

    Started by greglang, April 17th, 2018 03:11 AM
    • Replies: 0
    • Views: 131
    April 17th, 2018, 03:11 AM Go to last post
  18. Max v cpld programming

    Started by harry_blues, April 10th, 2018 09:44 PM
    #cpld, #maxv, #programming, #remote
    • Replies: 1
    • Views: 231
    April 16th, 2018, 10:36 PM Go to last post
    • Replies: 2
    • Views: 296
    April 16th, 2018, 01:13 AM Go to last post
  19. Cyclone IV E, transferring data using serial port

    Started by lukkio, April 1st, 2018 08:55 AM
    2 Pages
    1 2
    • Replies: 18
    • Views: 841
    April 15th, 2018, 03:19 PM Go to last post
  20. In Max II CPLD what is the content of UFM on power up?

    Started by chenbrlv, April 15th, 2018 12:22 AM
    cpld, max ii, ufm
    • Replies: 1
    • Views: 167
    April 15th, 2018, 02:14 AM Go to last post
  21. MAX 10 vs MAX II dynamic power consumption

    Started by Nownuri, April 14th, 2018 08:25 AM
    power
    • Replies: 1
    • Views: 193
    April 14th, 2018, 08:36 AM Go to last post
  22. Implicit MUX selector not drawn?

    Started by greglang, April 14th, 2018 07:17 AM
    • Replies: 1
    • Views: 165
    April 14th, 2018, 08:26 AM Go to last post
  23. Triple Speed Ethernet using DE2-115

    Started by elvissangwa, March 26th, 2018 02:08 PM
    • Replies: 3
    • Views: 446
    April 12th, 2018, 10:10 PM Go to last post
  24. Question Setting up PCIe Connection Cyclone V

    Started by milleral, April 12th, 2018 02:23 PM
    cyclone v, fpga, pcie
    • Replies: 0
    • Views: 175
    April 12th, 2018, 02:23 PM Go to last post
  25. EyeQ signal measurements

    Started by elisey, April 12th, 2018 06:27 AM
    • Replies: 0
    • Views: 198
    April 12th, 2018, 06:27 AM Go to last post

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