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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

    • Replies: 0
    • Views: 32
    Today, 04:29 AM Go to last post
  1. Compiling for EPM7128ATC

    Started by windfall, June 23rd, 2018 02:12 AM
    • Replies: 4
    • Views: 156
    Today, 03:36 AM Go to last post
  2. Max V CPLD Memory storage Query

    Started by jvpvcp88, Today 03:29 AM
    cpld, max v, memory
    • Replies: 0
    • Views: 37
    Today, 03:29 AM Go to last post
    • Replies: 1
    • Views: 88
    Today, 03:21 AM Go to last post
  3. Lightbulb Use Cyclone 10 LP to replace LVDS transceiver

    Started by william008, June 22nd, 2018 12:38 AM
    lvds cyclone10
    • Replies: 1
    • Views: 181
    Today, 01:42 AM Go to last post
  4. How to infer MLAB memory?

    Started by g_tushar, Yesterday 07:23 AM
    • Replies: 1
    • Views: 105
    Yesterday, 01:41 PM Go to last post
    • Replies: 1
    • Views: 87
    Yesterday, 01:36 PM Go to last post
  5. How to design ALM for Aria 10?

    Started by g_tushar, June 18th, 2018 04:26 PM
    • Replies: 4
    • Views: 378
    Yesterday, 07:21 AM Go to last post
  6. MAX10 UFM access time

    Started by dejan, May 28th, 2018 05:41 AM
    • Replies: 2
    • Views: 434
    Yesterday, 01:58 AM Go to last post
  7. Maximum inputs per LAB

    Started by eugenek, June 20th, 2018 03:18 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 478
    June 23rd, 2018, 06:22 PM Go to last post
  8. MAX7000AE consumes high power on a Max3000A design

    Started by andi6510, June 23rd, 2018 12:48 PM
    • Replies: 0
    • Views: 122
    June 23rd, 2018, 12:48 PM Go to last post
  9. Exclamation Problem with DE-10 nano Terasic KIT

    Started by allimos3, June 22nd, 2018 06:21 AM
    bitstream, error, load, nano10, reset
    • Replies: 2
    • Views: 242
    June 22nd, 2018, 12:20 PM Go to last post
    • Replies: 0
    • Views: 153
    June 22nd, 2018, 09:11 AM Go to last post
  10. Using Timequest to Analyze Processor Bus Interface

    Started by OG_973, June 21st, 2018 10:20 AM
    bus, processor, timequest
    • Replies: 6
    • Views: 345
    June 22nd, 2018, 07:56 AM Go to last post
  11. What is Altera postion about USB Blaster Clones?

    Started by luisf.rossi, April 11th, 2013 08:27 PM
    • Replies: 8
    • Views: 37,302
    June 21st, 2018, 09:14 PM Go to last post
  12. Unable to Flash EPCQ32A via SFL IP

    Started by theguenni, June 21st, 2018 01:28 AM
    • Replies: 2
    • Views: 221
    June 21st, 2018, 06:49 PM Go to last post
  13. Reg., DPCLK pins in MAX 10 FPGA

    Started by Thulasi11106, June 21st, 2018 12:48 AM
    • Replies: 1
    • Views: 195
    June 21st, 2018, 04:46 PM Go to last post
  14. Data Transfer from FPGA-to-HPS

    Started by andrew44, June 12th, 2018 11:54 AM
    2 Pages
    1 2
    • Replies: 17
    • Views: 925
    June 21st, 2018, 01:08 PM Go to last post
  15. Problem with Max 10 I've never seen before

    Started by ddavidd, June 18th, 2018 03:37 PM
    • Replies: 2
    • Views: 291
    June 21st, 2018, 01:05 PM Go to last post
  16. EMIF example design calibration fail on Stratix10

    Started by aabroug, June 21st, 2018 06:33 AM
    devkit, emif, stratix10
    • Replies: 2
    • Views: 210
    June 21st, 2018, 11:36 AM Go to last post
  17. Question MAX-10: IP core for UFM

    Started by SMS, June 10th, 2018 11:50 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 616
    June 21st, 2018, 06:54 AM Go to last post
  18. nStatus held low Cyclone IV EP4CE6E22

    Started by Labo_elec, June 18th, 2018 12:24 AM
    • Replies: 4
    • Views: 352
    June 21st, 2018, 12:47 AM Go to last post
    • Replies: 1
    • Views: 166
    June 21st, 2018, 12:10 AM Go to last post
  19. Post sdo file not generated in altera

    Started by shyamk, June 20th, 2018 02:46 AM
    • Replies: 2
    • Views: 206
    June 20th, 2018, 11:37 PM Go to last post
  20. Can I configure Cyclone V GT from Parallel Flash?

    Started by shy@navatek.com, June 13th, 2018 08:46 PM
    • Replies: 1
    • Views: 253
    June 20th, 2018, 11:29 PM Go to last post
  21. HMC pins in the CycloneV

    Started by serg1976, June 20th, 2018 10:06 AM
    • Replies: 1
    • Views: 206
    June 20th, 2018, 06:25 PM Go to last post
  22. PFL can not program my FLASH

    Started by xinbingma, May 17th, 2014 08:57 PM
    pfl
    • Replies: 1
    • Views: 14,451
    June 20th, 2018, 11:18 AM Go to last post
  23. About path delay in my FPGA

    Started by pan307398668, June 18th, 2018 07:38 PM
    path delay
    • Replies: 2
    • Views: 273
    June 20th, 2018, 03:39 AM Go to last post
  24. cyglone 5 gt interface for ads5263

    Started by thieulam, June 15th, 2016 02:28 AM
    • Replies: 4
    • Views: 1,393
    June 20th, 2018, 12:53 AM Go to last post

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