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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Config Flash EPCQ4A Cylone II

    Started by MarcFigliuolo, November 6th, 2017 02:56 AM
    • Replies: 5
    • Views: 1,150
    February 16th, 2018, 04:13 AM Go to last post
  2. Giving external input to Triple Speed Ethernet

    Started by beginner_EDA, April 3rd, 2014 05:57 AM
    3 Pages
    1 2 3
    • Replies: 25
    • Views: 23,108
    February 16th, 2018, 04:13 AM Go to last post
  3. Max10 NEEK for codec design with external master audio clock?

    Started by BillyZDSP, February 14th, 2018 07:42 PM
    • Replies: 1
    • Views: 145
    February 15th, 2018, 04:45 PM Go to last post
  4. Cyclone IV configuration from 1.8V SoC

    Started by jmce, February 13th, 2018 10:18 AM
    • Replies: 3
    • Views: 249
    February 15th, 2018, 05:38 AM Go to last post
  5. [TCL] query_collection -> why not working?

    Started by dmitryl, January 5th, 2018 04:36 AM
    • Replies: 1
    • Views: 362
    February 14th, 2018, 12:28 PM Go to last post
  6. Unhappy Quartus Prime Lite - Difficulties with simulation

    Started by swinchen, February 6th, 2018 09:22 AM
    • Replies: 9
    • Views: 498
    February 13th, 2018, 05:31 PM Go to last post
    • Replies: 0
    • Views: 169
    February 13th, 2018, 07:59 AM Go to last post
  7. Max10: ADC not working with .pof file

    Started by bienle, February 11th, 2018 11:20 PM
    adc, max10, pof
    • Replies: 3
    • Views: 199
    February 13th, 2018, 04:14 AM Go to last post
  8. question about Altera Cyclone 2

    Started by booleS, February 13th, 2018 01:31 AM
    • Replies: 1
    • Views: 154
    February 13th, 2018, 04:09 AM Go to last post
  9. Stratix IV security anti tamper fuse

    Started by remi.gauvin, January 30th, 2018 09:56 AM
    anti, fuse, security, tamper
    • Replies: 1
    • Views: 260
    February 12th, 2018, 11:27 PM Go to last post
  10. Terasic DE10 Standard kit and Intel Cyclone V SOC kit

    Started by manhha1402, February 3rd, 2018 03:05 PM
    • Replies: 1
    • Views: 280
    February 12th, 2018, 11:14 PM Go to last post
  11. Problem with SMBUS read stop bit

    Started by steven.mccoy, February 12th, 2018 01:19 PM
    • Replies: 0
    • Views: 138
    February 12th, 2018, 01:19 PM Go to last post
  12. CHANGE_EDREG JTAG instruction via a JAM file

    Started by kb_81, March 21st, 2007 04:14 PM
    • Replies: 4
    • Views: 64,486
    February 12th, 2018, 09:10 AM Go to last post
  13. MAX3000 : Downloading cable

    Started by fabrice, February 12th, 2018 12:03 AM
    max3000 cable
    • Replies: 2
    • Views: 169
    February 12th, 2018, 04:12 AM Go to last post
    • Replies: 2
    • Views: 279
    February 10th, 2018, 03:33 AM Go to last post
  14. Register vs Memory FPGA Cyclone V

    Started by john_altera, February 8th, 2018 09:53 AM
    • Replies: 3
    • Views: 919
    February 9th, 2018, 12:37 PM Go to last post
  15. Cyclone 10 GX EMIF crashes Quartus pro

    Started by mikezgrtf, January 30th, 2018 02:46 PM
    • Replies: 4
    • Views: 332
    February 8th, 2018, 08:28 AM Go to last post
  16. CycloneV FPGA

    Started by Suresh Kumar, February 8th, 2018 02:19 AM
    • Replies: 2
    • Views: 174
    February 8th, 2018, 06:40 AM Go to last post
  17. MAX10 mixed VCCIO for configuration pins

    Started by tnj195, January 16th, 2018 09:32 AM
    • Replies: 2
    • Views: 410
    February 8th, 2018, 04:55 AM Go to last post
  18. Combining pins to source / sink more current

    Started by falconri, February 7th, 2018 07:42 PM
    current, gpio, io pins, sink, source
    • Replies: 2
    • Views: 199
    February 8th, 2018, 02:38 AM Go to last post
  19. Need help with EPM7064BLC44

    Started by Pete16, February 7th, 2018 06:16 PM
    • Replies: 1
    • Views: 158
    February 7th, 2018, 10:05 PM Go to last post
  20. DE1 Board unable to "auto detect" (no hardware)

    Started by Ermanno, January 4th, 2018 02:28 PM
    • Replies: 4
    • Views: 524
    February 7th, 2018, 07:57 PM Go to last post
  21. Problem with MAX 10 pin assignment

    Started by hareesh9415, January 22nd, 2018 03:57 AM
    • Replies: 4
    • Views: 459
    February 7th, 2018, 07:49 PM Go to last post
  22. max10 adc sample point

    Started by qd0090, November 22nd, 2016 02:09 AM
    • Replies: 3
    • Views: 940
    February 7th, 2018, 06:27 PM Go to last post
  23. UART communication problem

    Started by NIDHI PANDA, February 7th, 2018 05:33 AM
    • Replies: 1
    • Views: 182
    February 7th, 2018, 06:57 AM Go to last post
  24. Arria 10 Dev Kit Max II and USB microcontroller

    Started by Ras, February 5th, 2018 02:47 AM
    • Replies: 5
    • Views: 314
    February 7th, 2018, 06:42 AM Go to last post
  25. fpga startup problem

    Started by new123, January 29th, 2018 03:50 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 669
    February 7th, 2018, 06:07 AM Go to last post
  26. Write protocol of EPC1/EPC1441

    Started by Arseniy, February 7th, 2018 03:16 AM
    • Replies: 0
    • Views: 149
    February 7th, 2018, 03:16 AM Go to last post
  27. MAX10 ADC Control Core - command_ready never high

    Started by xoox, February 5th, 2018 03:47 PM
    adc control core, command_ready, max10
    • Replies: 3
    • Views: 261
    February 6th, 2018, 05:13 PM Go to last post
  28. Cyclone 10 LP DDR IO-cell information

    Started by josyb, February 3rd, 2018 05:07 AM
    • Replies: 2
    • Views: 307
    February 6th, 2018, 12:55 AM Go to last post

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