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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

  1. What is wrong with Quartus II?

    Started by jylo, January 14th, 2018 03:07 AM
    3 Pages
    1 2 3
    • Replies: 20
    • Views: 541
    Today, 09:48 AM Go to last post
  2. Compilation Error

    Started by 1610dinesh, January 19th, 2018 09:55 PM
    • Replies: 1
    • Views: 74
    January 19th, 2018, 10:51 PM Go to last post
  3. Does anyone run Quartus on CentOS?

    Started by jeffw_00, December 20th, 2017 12:17 PM
    • Replies: 4
    • Views: 650
    January 19th, 2018, 11:52 AM Go to last post
  4. EDA Netlist Writer Crash with SystemVerilog

    Started by SR99, January 19th, 2018 10:05 AM
    • Replies: 0
    • Views: 65
    January 19th, 2018, 10:05 AM Go to last post
  5. twentynm_fp_mac_encrypted simulation in questasim

    Started by Nikitin, January 10th, 2018 02:30 AM
    • Replies: 2
    • Views: 229
    January 19th, 2018, 05:39 AM Go to last post
  6. Simulation Program for DE1-SoC board

    Started by battale, January 19th, 2018 05:34 AM
    • Replies: 0
    • Views: 62
    January 19th, 2018, 05:34 AM Go to last post
    • Replies: 0
    • Views: 72
    January 19th, 2018, 12:07 AM Go to last post
  7. fast forward tming closure for Stratix

    Started by ggeorgak, January 18th, 2018 11:32 PM
    hyper optimization, retiming, stratix10
    • Replies: 0
    • Views: 64
    January 18th, 2018, 11:32 PM Go to last post
    • Replies: 0
    • Views: 73
    January 18th, 2018, 11:21 AM Go to last post
  8. Question top level block symbol map question

    Started by jonolds, January 15th, 2018 10:20 PM
    • Replies: 6
    • Views: 215
    January 17th, 2018, 07:40 PM Go to last post
  9. [SignalTap] Storage Qualifier

    Started by dmitryl, January 15th, 2018 11:15 AM
    • Replies: 2
    • Views: 156
    January 17th, 2018, 06:03 PM Go to last post
    • Replies: 2
    • Views: 255
    January 16th, 2018, 06:44 AM Go to last post
    • Replies: 2
    • Views: 181
    January 15th, 2018, 12:13 PM Go to last post
  10. Pinconfig of the FPGA to HPS. Some eroors in IOBUF

    Started by sasi1922, January 11th, 2018 02:35 AM
    • Replies: 1
    • Views: 176
    January 15th, 2018, 06:34 AM Go to last post
    • Replies: 3
    • Views: 247
    January 15th, 2018, 05:56 AM Go to last post
  11. [Signal] unassigned node -> what does it mean?

    Started by dmitryl, January 15th, 2018 04:02 AM
    • Replies: 0
    • Views: 106
    January 15th, 2018, 04:02 AM Go to last post
  12. Angry DE10-Nano GHRD failure to generate

    Started by jonathanjo, January 9th, 2018 02:00 PM
    de10-nano quartus
    • Replies: 1
    • Views: 205
    January 14th, 2018, 10:12 AM Go to last post
  13. Remove recent files/projects

    Started by hdecharn, May 28th, 2016 01:10 AM
    • Replies: 4
    • Views: 1,250
    January 14th, 2018, 06:59 AM Go to last post
  14. Warning (14320): Synthesized away node -> what does it mean?

    Started by dmitryl, January 13th, 2018 03:22 PM
    • Replies: 1
    • Views: 176
    January 13th, 2018, 11:30 PM Go to last post
    • Replies: 0
    • Views: 129
    January 13th, 2018, 03:07 PM Go to last post
  15. RS232 UART not generated correctly in Quartus 17.0

    Started by corestar, May 27th, 2017 07:49 PM
    • Replies: 6
    • Views: 2,269
    January 12th, 2018, 02:17 AM Go to last post
  16. BluePrint Platform Designer

    Started by mohsin_qau, January 10th, 2018 01:47 AM
    • Replies: 4
    • Views: 278
    January 12th, 2018, 12:41 AM Go to last post
  17. running timing analysis without fitter first

    Started by ggeorgak, December 19th, 2017 04:50 AM
    fitter, quartus, timequest
    • Replies: 5
    • Views: 541
    January 11th, 2018, 06:24 PM Go to last post
  18. license for older Quartus II

    Started by flyingbirds, January 10th, 2018 11:48 AM
    12.0, license
    • Replies: 4
    • Views: 289
    January 11th, 2018, 01:46 PM Go to last post
  19. I need the vhdl code for IOBUF

    Started by sasi1922, January 11th, 2018 02:04 AM
    • Replies: 2
    • Views: 199
    January 11th, 2018, 01:16 PM Go to last post
  20. Inferring DSP in Arria 10

    Started by systom, January 11th, 2018 12:28 PM
    • Replies: 0
    • Views: 148
    January 11th, 2018, 12:28 PM Go to last post
  21. Problem with tcl automation script

    Started by andruwkoo, December 25th, 2017 06:51 AM
    quartus tcl
    • Replies: 2
    • Views: 445
    January 10th, 2018, 10:28 PM Go to last post
  22. SignalTap - II question

    Started by alteraaditya, January 9th, 2018 10:42 AM
    • Replies: 9
    • Views: 320
    January 9th, 2018, 02:41 PM Go to last post
  23. Rapid recompile

    Started by Witty, December 10th, 2009 02:22 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 58,562
    January 9th, 2018, 08:09 AM Go to last post
    • Replies: 1
    • Views: 188
    January 9th, 2018, 05:14 AM Go to last post

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