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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

  1. fast forward tming closure for Stratix

    Started by ggeorgak, Today 11:32 PM
    hyper optimization, retiming, stratix10
    • Replies: 0
    • Views: 1
    Today, 11:32 PM Go to last post
  2. What is wrong with Quartus II?

    Started by jylo, January 14th, 2018 03:07 AM
    2 Pages
    1 2
    • Replies: 17
    • Views: 440
    Today, 02:01 PM Go to last post
    • Replies: 0
    • Views: 41
    Today, 11:21 AM Go to last post
  3. Question top level block symbol map question

    Started by jonolds, January 15th, 2018 10:20 PM
    • Replies: 6
    • Views: 187
    Yesterday, 07:40 PM Go to last post
  4. [SignalTap] Storage Qualifier

    Started by dmitryl, January 15th, 2018 11:15 AM
    • Replies: 2
    • Views: 134
    Yesterday, 06:03 PM Go to last post
    • Replies: 2
    • Views: 232
    January 16th, 2018, 06:44 AM Go to last post
    • Replies: 2
    • Views: 163
    January 15th, 2018, 12:13 PM Go to last post
  5. Pinconfig of the FPGA to HPS. Some eroors in IOBUF

    Started by sasi1922, January 11th, 2018 02:35 AM
    • Replies: 1
    • Views: 163
    January 15th, 2018, 06:34 AM Go to last post
    • Replies: 3
    • Views: 226
    January 15th, 2018, 05:56 AM Go to last post
  6. [Signal] unassigned node -> what does it mean?

    Started by dmitryl, January 15th, 2018 04:02 AM
    • Replies: 0
    • Views: 92
    January 15th, 2018, 04:02 AM Go to last post
  7. Angry DE10-Nano GHRD failure to generate

    Started by jonathanjo, January 9th, 2018 02:00 PM
    de10-nano quartus
    • Replies: 1
    • Views: 186
    January 14th, 2018, 10:12 AM Go to last post
  8. Remove recent files/projects

    Started by hdecharn, May 28th, 2016 01:10 AM
    • Replies: 4
    • Views: 1,233
    January 14th, 2018, 06:59 AM Go to last post
  9. Warning (14320): Synthesized away node -> what does it mean?

    Started by dmitryl, January 13th, 2018 03:22 PM
    • Replies: 1
    • Views: 155
    January 13th, 2018, 11:30 PM Go to last post
    • Replies: 0
    • Views: 109
    January 13th, 2018, 03:07 PM Go to last post
  10. RS232 UART not generated correctly in Quartus 17.0

    Started by corestar, May 27th, 2017 07:49 PM
    • Replies: 6
    • Views: 2,231
    January 12th, 2018, 02:17 AM Go to last post
  11. BluePrint Platform Designer

    Started by mohsin_qau, January 10th, 2018 01:47 AM
    • Replies: 4
    • Views: 261
    January 12th, 2018, 12:41 AM Go to last post
  12. running timing analysis without fitter first

    Started by ggeorgak, December 19th, 2017 04:50 AM
    fitter, quartus, timequest
    • Replies: 5
    • Views: 522
    January 11th, 2018, 06:24 PM Go to last post
  13. license for older Quartus II

    Started by flyingbirds, January 10th, 2018 11:48 AM
    12.0, license
    • Replies: 4
    • Views: 270
    January 11th, 2018, 01:46 PM Go to last post
  14. I need the vhdl code for IOBUF

    Started by sasi1922, January 11th, 2018 02:04 AM
    • Replies: 2
    • Views: 184
    January 11th, 2018, 01:16 PM Go to last post
  15. Inferring DSP in Arria 10

    Started by systom, January 11th, 2018 12:28 PM
    • Replies: 0
    • Views: 123
    January 11th, 2018, 12:28 PM Go to last post
  16. Problem with tcl automation script

    Started by andruwkoo, December 25th, 2017 06:51 AM
    quartus tcl
    • Replies: 2
    • Views: 415
    January 10th, 2018, 10:28 PM Go to last post
  17. twentynm_fp_mac_encrypted simulation in questasim

    Started by Nikitin, January 10th, 2018 02:30 AM
    • Replies: 1
    • Views: 181
    January 10th, 2018, 03:10 AM Go to last post
  18. SignalTap - II question

    Started by alteraaditya, January 9th, 2018 10:42 AM
    • Replies: 9
    • Views: 281
    January 9th, 2018, 02:41 PM Go to last post
  19. Rapid recompile

    Started by Witty, December 10th, 2009 02:22 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 58,511
    January 9th, 2018, 08:09 AM Go to last post
    • Replies: 1
    • Views: 176
    January 9th, 2018, 05:14 AM Go to last post
  20. ALTPLL simulation model bug

    Started by patrickhl, January 8th, 2018 12:47 AM
    altpll, bug
    • Replies: 2
    • Views: 204
    January 8th, 2018, 04:27 PM Go to last post
    • Replies: 4
    • Views: 356
    January 8th, 2018, 01:38 PM Go to last post
  21. Question [QSYS] Wrong Avalon memory address generation?

    Started by wobbert, January 8th, 2018 02:03 AM
    • Replies: 1
    • Views: 170
    January 8th, 2018, 07:42 AM Go to last post
  22. Using relative include path with NativeLink?

    Started by fhw72, January 8th, 2018 07:28 AM
    • Replies: 0
    • Views: 165
    January 8th, 2018, 07:28 AM Go to last post
  23. [SDC] Input/Output delay for All ports -> script writing

    Started by dmitryl, January 5th, 2018 10:49 AM
    2 Pages
    1 2
    • Replies: 11
    • Views: 683
    January 8th, 2018, 03:58 AM Go to last post

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