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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

    • Replies: 1
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    Yesterday, 10:18 AM Go to last post
  1. TimeQuest command precedence for clock group

    Started by peter_King, Yesterday 07:02 AM
    • Replies: 0
    • Views: 79
    Yesterday, 07:02 AM Go to last post
    • Replies: 0
    • Views: 90
    Yesterday, 01:22 AM Go to last post
  2. Which licenses do I have checked out?

    Started by sadilek, December 14th, 2017 06:37 AM
    license, quartus 2
    • Replies: 1
    • Views: 192
    December 15th, 2017, 10:53 AM Go to last post
  3. Wherer does Quartus put files?

    Started by Doug314, December 14th, 2017 08:53 AM
    • Replies: 4
    • Views: 227
    December 15th, 2017, 08:11 AM Go to last post
  4. Print TDO on JTAG Chain Debugger

    Started by dams0622, December 15th, 2017 02:01 AM
    • Replies: 0
    • Views: 129
    December 15th, 2017, 02:01 AM Go to last post
  5. How to resolve this error?

    Started by Jerry, December 13th, 2017 07:20 PM
    • Replies: 2
    • Views: 216
    December 14th, 2017, 05:31 PM Go to last post
  6. Driver problem

    Started by Binome, December 14th, 2017 07:36 AM
    • Replies: 0
    • Views: 137
    December 14th, 2017, 07:36 AM Go to last post
  7. warning with on chip memory data items width

    Started by calagan, July 23rd, 2009 03:00 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 62,585
    December 13th, 2017, 08:51 AM Go to last post
  8. Cyclone 2 starter kit files

    Started by Gal13_private, December 11th, 2017 12:54 PM
    • Replies: 4
    • Views: 255
    December 12th, 2017, 01:15 PM Go to last post
  9. QuestaSim license usable in for ModelSim-altera

    Started by wobbert, December 11th, 2017 07:07 AM
    license, modelsim, questasim
    • Replies: 6
    • Views: 295
    December 12th, 2017, 11:09 AM Go to last post
  10. Warning: Tri-state nodes do not directly drive top-level pins

    Started by 888rt, December 11th, 2017 04:25 PM
    • Replies: 1
    • Views: 218
    December 11th, 2017, 04:44 PM Go to last post
    • Replies: 2
    • Views: 337
    December 10th, 2017, 01:17 AM Go to last post
  11. VHDL inout port in gate-level simulation

    Started by maxvenum, June 13th, 2017 04:15 PM
    • Replies: 5
    • Views: 1,326
    December 8th, 2017, 09:37 AM Go to last post
  12. Introducing delay in output pin

    Started by atrajesh, December 6th, 2017 02:49 AM
    • Replies: 9
    • Views: 498
    December 8th, 2017, 06:08 AM Go to last post
  13. How to ensure proper simulation in ModelSim

    Started by C1Ron, December 8th, 2017 01:25 AM
    • Replies: 6
    • Views: 394
    December 8th, 2017, 05:38 AM Go to last post
    • Replies: 0
    • Views: 172
    December 7th, 2017, 02:45 PM Go to last post
  14. Error when generating JESD204B Design EXample

    Started by alex-huang, December 7th, 2017 11:55 AM
    • Replies: 0
    • Views: 162
    December 7th, 2017, 11:55 AM Go to last post
    • Replies: 1
    • Views: 223
    December 7th, 2017, 10:50 AM Go to last post
  15. jtag debugger dosen't finds the connected cyclon ll processor

    Started by vrutha, December 1st, 2017 11:37 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 671
    December 7th, 2017, 03:02 AM Go to last post
  16. assign two clocks

    Started by Binome, November 30th, 2017 01:31 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 787
    December 6th, 2017, 11:47 PM Go to last post
  17. DDR differential pin assignments

    Started by Y0tsuya, December 4th, 2017 04:12 PM
    • Replies: 1
    • Views: 278
    December 5th, 2017, 06:05 PM Go to last post
  18. Cyclone V WYSIWYG primtives are broken :-(

    Started by lundril, July 28th, 2015 09:30 AM
    cyclone v, ddr3, wysiwyg
    • Replies: 4
    • Views: 2,488
    December 5th, 2017, 02:44 PM Go to last post
  19. Post PLL Simulation not working fine

    Started by XYZ, October 23rd, 2017 12:18 AM
    • Replies: 3
    • Views: 465
    December 5th, 2017, 12:59 AM Go to last post
    • Replies: 2
    • Views: 1,146
    December 5th, 2017, 12:56 AM Go to last post
  20. modelsim clock network stuck StX (gate level sim)

    Started by pmiach, December 3rd, 2017 03:07 AM
    • Replies: 6
    • Views: 384
    December 4th, 2017, 03:52 AM Go to last post
  21. TimeQuest Passes Hardware Fails

    Started by bangarren, December 3rd, 2017 11:40 PM
    • Replies: 0
    • Views: 250
    December 3rd, 2017, 11:40 PM Go to last post
  22. Neural Network

    Started by mohkredi, December 3rd, 2017 10:25 AM
    • Replies: 1
    • Views: 273
    December 3rd, 2017, 11:24 PM Go to last post
  23. how to dump routing elements in Quartus II

    Started by parcompute, April 13th, 2012 10:13 AM
    • Replies: 6
    • Views: 36,701
    December 1st, 2017, 04:23 PM Go to last post

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