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Forum: Quartus II and EDA Tools Discussion

A place to discuss topics related to Altera's development tool as well as 3rd Party EDA tools for synthesis and simulation

  1. unused prn/clrn inputs

    Started by Ray Random, July 5th, 2018 03:02 AM
    • Replies: 3
    • Views: 235
    Yesterday, 10:57 PM Go to last post
    • Replies: 0
    • Views: 52
    Yesterday, 11:58 AM Go to last post
    • Replies: 2
    • Views: 68
    Yesterday, 11:35 AM Go to last post
  2. signaltap compile error

    Started by super-1943, August 23rd, 2015 10:01 PM
    • Replies: 2
    • Views: 1,811
    Yesterday, 10:28 AM Go to last post
    • Replies: 6
    • Views: 552
    Yesterday, 01:31 AM Go to last post
  3. Error 332000 when using DCFIFOs in Qsys during build

    Started by DocJava, March 24th, 2017 03:42 PM
    • Replies: 4
    • Views: 2,086
    July 14th, 2018, 04:03 AM Go to last post
  4. Quartus ip-generate command: List of available components

    Started by wobbert, July 13th, 2018 08:09 AM
    arria v gz, ip-generate, tbed
    • Replies: 0
    • Views: 134
    July 13th, 2018, 08:09 AM Go to last post
    • Replies: 3
    • Views: 246
    July 12th, 2018, 10:37 PM Go to last post
  5. Modelsim hanging trying to compile Stratix IP

    Started by AndyN, July 2nd, 2018 09:41 AM
    ip compilation, modelsim, stratix
    • Replies: 6
    • Views: 397
    July 12th, 2018, 09:21 AM Go to last post
    • Replies: 4
    • Views: 1,262
    July 12th, 2018, 07:00 AM Go to last post
    • Replies: 0
    • Views: 128
    July 12th, 2018, 03:41 AM Go to last post
    • Replies: 0
    • Views: 142
    July 11th, 2018, 10:48 PM Go to last post
  6. Problems with graphics on Quartus 17.1 lite

    Started by joshuajeromebrooks, March 14th, 2018 06:41 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 1,639
    July 11th, 2018, 11:48 AM Go to last post
    • Replies: 0
    • Views: 116
    July 11th, 2018, 08:49 AM Go to last post
  7. IEEE 1735 encryption in Quartus

    Started by ybajwa, July 11th, 2018 04:30 AM
    ieee1735
    • Replies: 0
    • Views: 107
    July 11th, 2018, 04:30 AM Go to last post
  8. How do I connect 4, 4-bit, busses each to an LPM_MUX?

    Started by aspepp, July 10th, 2018 09:25 AM
    • Replies: 1
    • Views: 173
    July 10th, 2018, 11:24 PM Go to last post
  9. Quartus Pro and post-synth QDB for IP cores: Covering more than a single FPGA

    Started by eli, February 24th, 2018 08:10 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 1,621
    July 10th, 2018, 03:33 AM Go to last post
  10. QVM netlist generated by Quartus: Safe for use?

    Started by eli, July 9th, 2018 08:15 PM
    • Replies: 0
    • Views: 104
    July 9th, 2018, 08:15 PM Go to last post
    • Replies: 8
    • Views: 543
    July 9th, 2018, 05:52 AM Go to last post
  11. Does the v17 Quartus Prime support old v13.1 NIOS ?

    Started by Terry.Fan, July 8th, 2018 08:40 PM
    • Replies: 1
    • Views: 149
    July 8th, 2018, 10:00 PM Go to last post
  12. Cannot edit the generated PLL Intel FPGA IP v18.0

    Started by zeahr, June 4th, 2018 08:49 PM
    • Replies: 8
    • Views: 1,019
    July 6th, 2018, 04:18 PM Go to last post
  13. BlasterII driver installed but Quartus not detecting

    Started by davidg, July 6th, 2018 03:35 PM
    • Replies: 0
    • Views: 163
    July 6th, 2018, 03:35 PM Go to last post
  14. Quartus 18 MegaWizard issue

    Started by krtkr, May 24th, 2018 06:31 AM
    • Replies: 7
    • Views: 1,208
    July 5th, 2018, 08:35 PM Go to last post
  15. OpenCore Plus IP Licensing

    Started by battersea, July 2nd, 2018 03:23 AM
    • Replies: 2
    • Views: 260
    July 4th, 2018, 04:46 AM Go to last post
  16. can't launch design space explorer

    Started by roymesi, July 3rd, 2018 11:08 AM
    • Replies: 1
    • Views: 206
    July 3rd, 2018, 12:00 PM Go to last post
  17. High logic bloat for Platform Designer Interconnect

    Started by dzos_pf, July 3rd, 2018 03:54 AM
    • Replies: 1
    • Views: 224
    July 3rd, 2018, 10:11 AM Go to last post
  18. Can't Access JTAG Chain Programmer Failed

    Started by andrew44, July 2nd, 2018 12:38 PM
    • Replies: 4
    • Views: 318
    July 3rd, 2018, 06:15 AM Go to last post
    • Replies: 0
    • Views: 178
    July 3rd, 2018, 12:48 AM Go to last post
    • Replies: 2
    • Views: 210
    July 2nd, 2018, 10:47 AM Go to last post
  19. Input signal pin as global clock

    Started by edinsam, July 1st, 2018 02:09 AM
    clock, quartus, vhdl
    • Replies: 3
    • Views: 301
    July 2nd, 2018, 10:04 AM Go to last post

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