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Forum: Verilog and System Verilog

A place to ask Verilog and System Verilog questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:48 PM
    • Replies: 0
    • Views: 45,160
    October 5th, 2012, 12:48 PM Go to last post
  1. Instantiating VHDL entity in Systemverilog

    Started by mugginsac, June 15th, 2018 08:26 AM
    • Replies: 4
    • Views: 218
    Yesterday, 02:31 PM Go to last post
  2. Strange code behavior, once it works, once not.

    Started by kgotfryd, March 30th, 2018 11:13 AM
    • Replies: 1
    • Views: 687
    June 16th, 2018, 09:04 AM Go to last post
  3. Question Verilog Coding

    Started by anivan, June 13th, 2018 11:53 AM
    • Replies: 2
    • Views: 222
    June 13th, 2018, 02:11 PM Go to last post
  4. SystemVerilog logic type as bidir

    Started by click_er, June 6th, 2018 12:40 PM
    • Replies: 3
    • Views: 349
    June 6th, 2018, 07:43 PM Go to last post
  5. Interfaces and Synthesis

    Started by erim, June 1st, 2018 09:58 AM
    • Replies: 2
    • Views: 442
    June 4th, 2018, 05:51 AM Go to last post
  6. Latha

    Started by Latha P, June 2nd, 2018 10:12 AM
    • Replies: 2
    • Views: 331
    June 4th, 2018, 12:50 AM Go to last post
  7. Lightbulb Verilog coding issue

    Started by Nauman Memon, May 30th, 2018 05:09 PM
    • Replies: 6
    • Views: 549
    June 1st, 2018, 04:23 AM Go to last post
  8. SPI slave clock crossing domain?

    Started by JackBK, May 17th, 2018 08:25 PM
    • Replies: 8
    • Views: 1,063
    May 27th, 2018, 08:00 PM Go to last post
  9. flop-flop simulation in ModelSim

    Started by demsp, May 16th, 2018 09:55 PM
    • Replies: 6
    • Views: 803
    May 18th, 2018, 05:53 AM Go to last post
    • Replies: 6
    • Views: 977
    May 8th, 2018, 06:43 AM Go to last post
    • Replies: 7
    • Views: 1,104
    April 23rd, 2018, 10:07 PM Go to last post
    • Replies: 0
    • Views: 623
    April 11th, 2018, 06:34 AM Go to last post
  10. pi controller i verilog

    Started by kkp, March 23rd, 2018 01:21 PM
    • Replies: 1
    • Views: 633
    April 10th, 2018, 01:13 PM Go to last post
  11. Mixed blocking and non- with always@ ?

    Started by greglang, April 10th, 2018 03:05 AM
    • Replies: 4
    • Views: 678
    April 10th, 2018, 11:20 AM Go to last post
  12. Question delay a signal by several clk cycles in verilog

    Started by handaxiao, April 5th, 2018 04:28 PM
    • Replies: 1
    • Views: 568
    April 5th, 2018, 08:54 PM Go to last post
  13. Need help designing a Custom IP with Avalon Slave Interface

    Started by mh9840, March 31st, 2018 02:17 AM
    • Replies: 2
    • Views: 881
    March 31st, 2018, 12:08 PM Go to last post
  14. LED to clock in Register

    Started by demsp, March 17th, 2018 01:29 PM
    2 Pages
    1 2
    • Replies: 15
    • Views: 1,624
    March 25th, 2018, 08:56 AM Go to last post
  15. changing output from two always blocks

    Started by Bobdoe, March 20th, 2018 03:44 PM
    • Replies: 3
    • Views: 1,011
    March 22nd, 2018, 10:22 AM Go to last post
    • Replies: 0
    • Views: 679
    March 15th, 2018, 04:07 PM Go to last post
  16. adc_mic_lcd demonstration on NEEK max10

    Started by Djcx, March 14th, 2018 06:45 AM
    • Replies: 1
    • Views: 632
    March 15th, 2018, 06:04 AM Go to last post
  17. illegal inout port connections in vsim 3053

    Started by rainbow, March 14th, 2018 07:59 AM
    • Replies: 1
    • Views: 719
    March 14th, 2018, 09:54 AM Go to last post
  18. Parameter type not supported?

    Started by rgarciaf071, February 28th, 2018 07:55 AM
    • Replies: 5
    • Views: 1,528
    March 5th, 2018, 11:13 PM Go to last post
  19. task vs always

    Started by rock bog, March 3rd, 2018 12:41 PM
    • Replies: 4
    • Views: 1,023
    March 5th, 2018, 12:47 AM Go to last post
    • Replies: 0
    • Views: 667
    March 2nd, 2018, 01:47 PM Go to last post
  20. PI loop filter logic in Verilog

    Started by rock bog, February 23rd, 2018 07:19 AM
    • Replies: 3
    • Views: 1,223
    February 27th, 2018, 01:19 AM Go to last post
  21. How to use SCLR port of an Flip flop in Verilog?

    Started by zubeyr, February 21st, 2018 08:57 AM
    • Replies: 1
    • Views: 892
    February 22nd, 2018, 02:50 AM Go to last post
  22. Array Declaration cases

    Started by dmitryl, February 19th, 2018 10:34 AM
    • Replies: 2
    • Views: 836
    February 19th, 2018, 02:09 PM Go to last post
  23. Look Up Table of enum types -> declaration + usage -> how to?

    Started by dmitryl, February 19th, 2018 10:38 AM
    • Replies: 0
    • Views: 667
    February 19th, 2018, 10:38 AM Go to last post
  24. FIFO Works fine on EDAPlayground but not Quartus

    Started by ch701builder, February 16th, 2018 09:18 AM
    • Replies: 5
    • Views: 1,133
    February 16th, 2018, 04:29 PM Go to last post
  25. "j" is not a constant in verilog for loop addition

    Started by rozsatib, February 15th, 2018 08:48 AM
    • Replies: 3
    • Views: 1,078
    February 15th, 2018, 11:50 PM Go to last post

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