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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 12:52 PM
    • Replies: 6
    • Views: 43,747
    October 28th, 2015, 12:36 PM Go to last post
  1. Replacing a process with 1-port RAM

    Started by NovNov, April 26th, 2017 04:55 PM
    ram, rom, stepper, vhdl
    • Replies: 3
    • Views: 149
    April 28th, 2017, 10:04 PM Go to last post
  2. altera_attribute for regional_clock

    Started by jwiesemann, April 27th, 2017 12:54 AM
    altera_attribute, gloabl_signal, regional clock, syntax
    • Replies: 2
    • Views: 139
    April 28th, 2017, 04:43 PM Go to last post
  3. How to use Shared Variable

    Started by wanjoe, March 2nd, 2017 03:55 AM
    • Replies: 5
    • Views: 593
    April 28th, 2017, 07:01 AM Go to last post
  4. Asynchronous pulse generator code rising edge

    Started by jonhmiller, April 26th, 2017 02:59 PM
    • Replies: 8
    • Views: 256
    April 27th, 2017, 11:48 AM Go to last post
  5. VHDL Coding Help - Altera DE1 Board

    Started by sangamsaga, April 26th, 2017 04:05 PM
    • Replies: 1
    • Views: 115
    April 26th, 2017, 10:54 PM Go to last post
  6. ARRAY with a dynamic range

    Started by yossiwf, April 24th, 2017 05:34 AM
    • Replies: 3
    • Views: 241
    April 25th, 2017, 12:06 AM Go to last post
  7. variable initialization help

    Started by zhbai, April 22nd, 2017 01:41 PM
    • Replies: 9
    • Views: 419
    April 24th, 2017, 11:27 PM Go to last post
  8. Post RAM property help

    Started by zhbai, April 11th, 2017 02:28 PM
    • Replies: 7
    • Views: 537
    April 13th, 2017, 01:14 PM Go to last post
  9. Read in external ADC values

    Started by Christoph1990, April 8th, 2017 08:59 AM
    • Replies: 4
    • Views: 525
    April 11th, 2017, 08:46 PM Go to last post
  10. Question Clocking is too complex - error

    Started by Pickwick, April 8th, 2017 05:55 AM
    • Replies: 3
    • Views: 425
    April 8th, 2017, 02:19 PM Go to last post
  11. integer overflow

    Started by jreinauld, April 7th, 2017 05:43 AM
    • Replies: 2
    • Views: 339
    April 7th, 2017, 08:23 AM Go to last post
  12. Issues with access to array of accesses

    Started by jreinauld, April 5th, 2017 09:21 AM
    • Replies: 2
    • Views: 353
    April 6th, 2017, 12:01 AM Go to last post
  13. Parallel VHDL

    Started by FINCH1, March 26th, 2017 11:45 AM
    • Replies: 8
    • Views: 693
    April 4th, 2017, 12:33 AM Go to last post
  14. Multiple RAM with different mif file

    Started by zhbai, March 28th, 2017 08:39 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 707
    March 31st, 2017, 05:14 PM Go to last post
  15. Unhappy Error 10500 Help me !!!

    Started by milena199, March 28th, 2017 02:08 AM
    10500, error
    • Replies: 3
    • Views: 408
    March 30th, 2017, 09:46 PM Go to last post
    • Replies: 1
    • Views: 317
    March 28th, 2017, 02:00 AM Go to last post
  16. Post Synthesis simulation fails, problem with RTL?

    Started by tmny277, March 26th, 2017 07:14 PM
    • Replies: 3
    • Views: 428
    March 27th, 2017, 11:17 AM Go to last post
  17. Signal not assigned in init state

    Started by PuqmaStar, March 21st, 2017 08:20 PM
    2 Pages
    1 2
    • Replies: 16
    • Views: 1,271
    March 25th, 2017, 04:58 PM Go to last post
  18. VHDL "Quantum" bug

    Started by javieralso, March 17th, 2017 04:41 AM
    • Replies: 4
    • Views: 482
    March 21st, 2017, 07:07 AM Go to last post
  19. UART VDHL code not working getting only garbage values

    Started by G.Ornil, March 17th, 2017 01:26 AM
    de0-nani-soc, fpga cyclone v, uart, vhdl
    • Replies: 1
    • Views: 413
    March 20th, 2017, 01:08 PM Go to last post
  20. Edge detection asynchronous signal fails

    Started by PuqmaStar, March 18th, 2017 06:15 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 724
    March 20th, 2017, 12:12 AM Go to last post
  21. Bi Directional pins

    Started by tmny277, February 18th, 2017 01:20 PM
    2 Pages
    1 2
    • Replies: 10
    • Views: 838
    March 18th, 2017, 02:49 PM Go to last post
  22. VHDL 2008: Error (10500) in conditional assignment

    Started by arne, March 13th, 2017 01:49 AM
    vhdl-2008
    • Replies: 5
    • Views: 540
    March 13th, 2017, 03:00 AM Go to last post
  23. Type problem? Compiler doesn't help me!

    Started by Josť, March 9th, 2017 10:06 AM
    • Replies: 5
    • Views: 552
    March 10th, 2017, 10:43 PM Go to last post
    • Replies: 2
    • Views: 391
    March 6th, 2017, 10:19 AM Go to last post
  24. Question Long FIR Filter

    Started by shauk, March 6th, 2017 02:06 AM
    • Replies: 5
    • Views: 450
    March 6th, 2017, 03:32 AM Go to last post
  25. Interrupt detection

    Started by john7, March 2nd, 2017 12:13 AM
    • Replies: 1
    • Views: 325
    March 2nd, 2017, 03:33 AM Go to last post
  26. Buffering a signal.

    Started by john7, March 1st, 2017 02:36 AM
    • Replies: 8
    • Views: 627
    March 1st, 2017, 07:31 AM Go to last post
  27. When to reset a signal.

    Started by john7, February 28th, 2017 06:04 AM
    • Replies: 5
    • Views: 533
    February 28th, 2017, 11:15 PM Go to last post
  28. Can't resolve multiple constant drivers

    Started by john7, February 27th, 2017 12:45 AM
    2 Pages
    1 2
    • Replies: 12
    • Views: 729
    February 28th, 2017, 02:02 AM Go to last post

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