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Forum: VHDL

A place to ask VHDL questions

  1. Sticky Thread Sticky: *** Read Me ***

    Started by BadOmen, October 5th, 2012 01:52 PM
    • Replies: 6
    • Views: 46,285
    October 28th, 2015, 01:36 PM Go to last post
    • Replies: 5
    • Views: 61
    Today, 08:26 AM Go to last post
    • Replies: 0
    • Views: 54
    Yesterday, 09:32 AM Go to last post
  1. default signal assignments

    Started by ggeorgak, November 21st, 2017 05:07 AM
    default signal, quartus, vhdl
    • Replies: 1
    • Views: 119
    November 21st, 2017, 05:17 AM Go to last post
  2. LEDs in interleaving method

    Started by mushussain, November 5th, 2017 10:15 PM
    • Replies: 6
    • Views: 736
    November 12th, 2017, 06:27 AM Go to last post
  3. how to map many ports to a vector/array ?

    Started by dmitryl, November 8th, 2017 07:32 AM
    • Replies: 3
    • Views: 277
    November 8th, 2017, 10:29 AM Go to last post
  4. Dividing a negative number

    Started by yossiwf, October 29th, 2017 07:39 AM
    • Replies: 5
    • Views: 551
    November 3rd, 2017, 02:53 PM Go to last post
    • Replies: 8
    • Views: 907
    November 3rd, 2017, 02:33 PM Go to last post
  5. State machine counter problems

    Started by jonhmiller, October 26th, 2017 09:51 AM
    • Replies: 3
    • Views: 453
    October 26th, 2017, 01:51 PM Go to last post
  6. Combinational Loop In VHDL synthesis

    Started by Reza M. Shahshahani, October 3rd, 2017 07:22 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 1,556
    October 24th, 2017, 08:06 PM Go to last post
  7. Meeting timing requirements with async signal.

    Started by Vinícius Lambardozzi, October 23rd, 2017 03:23 AM
    mips, processor design, ram, timing
    • Replies: 1
    • Views: 342
    October 23rd, 2017, 05:26 AM Go to last post
  8. Call a function from a function in VHDL

    Started by abenitez, October 13th, 2017 06:36 AM
    • Replies: 9
    • Views: 1,018
    October 16th, 2017, 09:47 AM Go to last post
  9. Unhappy Mod5 Counter

    Started by antonio.abela, October 14th, 2017 03:45 AM
    • Replies: 1
    • Views: 400
    October 16th, 2017, 03:27 AM Go to last post
  10. High-Z on Differential Port

    Started by afronteau, October 13th, 2017 06:55 AM
    an754, differential, high-z, mipi
    • Replies: 1
    • Views: 405
    October 14th, 2017, 02:40 AM Go to last post
  11. How to use Shared Variable

    Started by wanjoe, March 2nd, 2017 04:55 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 4,732
    October 6th, 2017, 07:32 AM Go to last post
  12. Asynchronous FIFO

    Started by fm1990, October 6th, 2017 03:50 AM
    • Replies: 1
    • Views: 402
    October 6th, 2017, 05:59 AM Go to last post
  13. Cascaded Interpolation Filter and Restricted Fmax

    Started by shauk, July 19th, 2017 02:32 AM
    cascadefilter
    • Replies: 5
    • Views: 1,796
    October 4th, 2017, 09:15 PM Go to last post
  14. Adjustable frequency generator

    Started by kaamil115, September 23rd, 2017 04:59 AM
    • Replies: 5
    • Views: 1,066
    September 24th, 2017, 04:29 PM Go to last post
  15. Unhappy Implement mux using for loop

    Started by JeanValjean, September 15th, 2017 01:32 AM
    loop, mux, synthesis
    • Replies: 8
    • Views: 1,352
    September 16th, 2017, 01:49 AM Go to last post
  16. problem with type matching

    Started by lukasliekens, September 13th, 2017 11:35 AM
    component, instantiation, integer, modelsim, type
    • Replies: 6
    • Views: 985
    September 15th, 2017, 10:51 AM Go to last post
  17. using typedef intput argument for function

    Started by bienle, September 13th, 2017 06:16 AM
    vhdl; function;
    • Replies: 3
    • Views: 736
    September 13th, 2017, 11:56 PM Go to last post
  18. Question VHDL Model for MIPS Processor

    Started by irontitan76, May 3rd, 2013 10:47 PM
    4stage, mips, pipelined
    • Replies: 3
    • Views: 32,350
    September 12th, 2017, 11:43 AM Go to last post
  19. Problem with resolving signals in vhdl

    Started by lukasliekens, September 6th, 2017 11:00 AM
    integer, resolving signals, testbench, unresolved, vhdl
    • Replies: 6
    • Views: 1,233
    September 11th, 2017, 01:16 PM Go to last post
    • Replies: 1
    • Views: 576
    September 10th, 2017, 09:00 AM Go to last post
  20. how to calculate sin inverse (ARCSIN) in VHDL?

    Started by G.Ornil, June 29th, 2017 02:28 AM
    2 Pages
    1 2
    vhdl arcsin
    • Replies: 10
    • Views: 3,623
    September 4th, 2017, 05:53 PM Go to last post
    • Replies: 2
    • Views: 988
    September 4th, 2017, 05:47 PM Go to last post
  21. Question frequency meter on cyclone IV E ,without display frequency

    Started by SmErT, August 21st, 2017 03:46 AM
    • Replies: 5
    • Views: 1,338
    August 22nd, 2017, 01:11 AM Go to last post
  22. StateMachine States in SignalTAP

    Started by fpgaengineerfrankfurt, August 15th, 2017 04:42 AM
    • Replies: 2
    • Views: 996
    August 15th, 2017, 09:46 PM Go to last post
    • Replies: 2
    • Views: 1,126
    August 4th, 2017, 03:45 AM Go to last post
  23. LFSR doesn't generate random values during simulation Ask

    Started by learn1, August 4th, 2017 12:06 AM
    galois, lfsr, vhdl
    • Replies: 7
    • Views: 1,565
    August 4th, 2017, 01:21 AM Go to last post
  24. Another 10482 VHDL error

    Started by jnuckols, July 31st, 2017 05:13 AM
    10482
    • Replies: 2
    • Views: 983
    July 31st, 2017, 06:19 AM Go to last post

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