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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 529
    • Posts: 1,985
  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 222
    • Posts: 578

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  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    • Threads: 16
    • Posts: 44

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  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    • Threads: 76
    • Posts: 265
  5. A place to discuss booting SoC devices and the bootloader that makes this happen

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    Forum Statistics:

    • Threads: 90
    • Posts: 347

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  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 12:29 PM
    • Replies: 0
    • Views: 10,779
    January 27th, 2015, 12:29 PM Go to last post
    • Replies: 2
    • Views: 141
    January 17th, 2018, 02:45 PM Go to last post
  1. Question HPS SPI Master with more than 4 Slave Selects

    Started by Designer777, January 12th, 2018 06:42 AM
    arria 10, slave select, soc, spi, spi master controller
    • Replies: 1
    • Views: 188
    January 13th, 2018, 08:20 PM Go to last post
  2. de10 nano ethernet phy clock loanio

    Started by letrend, January 12th, 2018 05:28 PM
    • Replies: 0
    • Views: 136
    January 12th, 2018, 05:28 PM Go to last post
    • Replies: 7
    • Views: 471
    January 8th, 2018, 10:44 AM Go to last post
  3. Memory map error in software program

    Started by karthik.k, January 7th, 2018 09:31 PM
    • Replies: 0
    • Views: 359
    January 7th, 2018, 09:31 PM Go to last post
  4. Set initial value at beginning

    Started by Doug314, December 30th, 2017 08:25 AM
    • Replies: 4
    • Views: 536
    January 1st, 2018, 07:15 AM Go to last post
  5. 5CSEBA2 Cyclone V SOC HPS-DDR3 w/ECC

    Started by vanlandingham10, December 18th, 2017 01:25 PM
    5cseba2, cyclone v, ddr3, ecc
    • Replies: 0
    • Views: 332
    December 18th, 2017, 01:25 PM Go to last post
    • Replies: 2
    • Views: 535
    December 14th, 2017, 02:20 AM Go to last post
  6. creating custom multiple registers

    Started by smruthi, December 12th, 2017 05:00 AM
    custom component, nios2
    • Replies: 3
    • Views: 572
    December 12th, 2017, 04:46 PM Go to last post
  7. Address Span Extender

    Started by MUTHUVENKATESH, November 30th, 2017 02:08 AM
    • Replies: 1
    • Views: 614
    December 10th, 2017, 03:42 AM Go to last post
  8. UART encoding issues

    Started by koded, December 8th, 2017 09:16 AM
    • Replies: 1
    • Views: 431
    December 9th, 2017, 02:54 AM Go to last post
  9. Fpga -qt

    Started by KANZALI, December 3rd, 2017 04:22 AM
    • Replies: 1
    • Views: 479
    December 3rd, 2017, 07:23 PM Go to last post
    • Replies: 1
    • Views: 544
    December 1st, 2017, 11:46 PM Go to last post
  10. Tristate bridge controller parameters

    Started by berretto77, November 30th, 2017 05:54 AM
    • Replies: 0
    • Views: 462
    November 30th, 2017, 05:54 AM Go to last post
  11. Verify functionality of design in arria 10 SoC

    Started by karthik.k, November 29th, 2017 01:50 AM
    • Replies: 0
    • Views: 906
    November 29th, 2017, 01:50 AM Go to last post
  12. Cyclone V SOC F2S Arbitration

    Started by shaiko, November 24th, 2017 04:14 AM
    • Replies: 0
    • Views: 522
    November 24th, 2017, 04:14 AM Go to last post
  13. Cyclone V HPS Memory

    Started by koded, November 18th, 2017 02:32 PM
    • Replies: 2
    • Views: 643
    November 20th, 2017, 11:08 PM Go to last post
    • Replies: 4
    • Views: 2,152
    November 18th, 2017, 09:08 PM Go to last post
  14. Cyclone V, sharing memory between FPGA and HPS

    Started by skliarovartem, November 13th, 2017 04:21 AM
    • Replies: 3
    • Views: 613
    November 13th, 2017, 10:06 AM Go to last post
    • Replies: 2
    • Views: 721
    November 12th, 2017, 01:13 PM Go to last post
  15. Qsys Custom component Error

    Started by Marco Lobba, August 8th, 2017 08:29 AM
    • Replies: 3
    • Views: 1,445
    November 10th, 2017, 03:49 AM Go to last post
  16. Interfacing uOLED Display to Cyclone V HPS

    Started by kba, November 6th, 2017 09:04 AM
    • Replies: 1
    • Views: 517
    November 8th, 2017, 11:22 PM Go to last post
  17. arria 10 jtag problem while using ds5

    Started by hl8316, August 23rd, 2017 07:30 PM
    • Replies: 4
    • Views: 1,442
    November 7th, 2017, 04:21 AM Go to last post
    • Replies: 1
    • Views: 626
    November 2nd, 2017, 11:45 AM Go to last post
  18. mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface

    Started by slh47, October 30th, 2017 02:38 AM
    • Replies: 2
    • Views: 642
    October 30th, 2017, 11:52 AM Go to last post
  19. DMA read timeout while using PL330?

    Started by Brillow, May 12th, 2016 07:44 AM
    • Replies: 4
    • Views: 2,888
    October 27th, 2017, 01:39 PM Go to last post
    • Replies: 4
    • Views: 2,612
    October 27th, 2017, 07:43 AM Go to last post
  20. Question FPGA to SDRAM AXI Transfer

    Started by ariefgrand, October 6th, 2017 08:04 AM
    arria, axi, sdram
    • Replies: 3
    • Views: 1,116
    October 27th, 2017, 01:21 AM Go to last post
    • Replies: 0
    • Views: 514
    October 24th, 2017, 12:26 AM Go to last post
  21. Getting Error with DE0-nano-soc [making u-boot.img]

    Started by jongyun23, August 31st, 2017 11:24 PM
    • Replies: 2
    • Views: 1,072
    October 16th, 2017, 01:43 AM Go to last post

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