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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 518
    • Posts: 1,954
  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 216
    • Posts: 568

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  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    • Threads: 16
    • Posts: 44

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  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    Forum Statistics:

    • Threads: 71
    • Posts: 253
  5. A place to discuss booting SoC devices and the bootloader that makes this happen

    Forum Actions:

    Forum Statistics:

    • Threads: 87
    • Posts: 333
  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 12:29 PM
    • Replies: 0
    • Views: 10,501
    January 27th, 2015, 12:29 PM Go to last post
  1. Cyclone V SOC F2S Arbitration

    Started by shaiko, Today 04:14 AM
    • Replies: 0
    • Views: 7
    Today, 04:14 AM Go to last post
  2. Cyclone V HPS Memory

    Started by koded, November 18th, 2017 02:32 PM
    • Replies: 2
    • Views: 177
    November 20th, 2017, 11:08 PM Go to last post
    • Replies: 4
    • Views: 1,472
    November 18th, 2017, 09:08 PM Go to last post
  3. Cyclone V, sharing memory between FPGA and HPS

    Started by skliarovartem, November 13th, 2017 04:21 AM
    • Replies: 3
    • Views: 231
    November 13th, 2017, 10:06 AM Go to last post
    • Replies: 2
    • Views: 332
    November 12th, 2017, 01:13 PM Go to last post
  4. Qsys Custom component Error

    Started by Marco Lobba, August 8th, 2017 08:29 AM
    • Replies: 3
    • Views: 936
    November 10th, 2017, 03:49 AM Go to last post
  5. Interfacing uOLED Display to Cyclone V HPS

    Started by kba, November 6th, 2017 09:04 AM
    • Replies: 1
    • Views: 232
    November 8th, 2017, 11:22 PM Go to last post
  6. arria 10 jtag problem while using ds5

    Started by hl8316, August 23rd, 2017 07:30 PM
    • Replies: 4
    • Views: 904
    November 7th, 2017, 04:21 AM Go to last post
    • Replies: 1
    • Views: 294
    November 2nd, 2017, 11:45 AM Go to last post
  7. mSGDMA transfer from DDR3 using FPGA2HPS-SDRAM interface

    Started by slh47, October 30th, 2017 02:38 AM
    • Replies: 2
    • Views: 344
    October 30th, 2017, 11:52 AM Go to last post
  8. DMA read timeout while using PL330?

    Started by Brillow, May 12th, 2016 07:44 AM
    • Replies: 4
    • Views: 2,454
    October 27th, 2017, 01:39 PM Go to last post
    • Replies: 4
    • Views: 2,072
    October 27th, 2017, 07:43 AM Go to last post
  9. Question FPGA to SDRAM AXI Transfer

    Started by ariefgrand, October 6th, 2017 08:04 AM
    arria, axi, sdram
    • Replies: 3
    • Views: 697
    October 27th, 2017, 01:21 AM Go to last post
    • Replies: 0
    • Views: 276
    October 24th, 2017, 12:26 AM Go to last post
  10. Getting Error with DE0-nano-soc [making u-boot.img]

    Started by jongyun23, August 31st, 2017 11:24 PM
    • Replies: 2
    • Views: 712
    October 16th, 2017, 01:43 AM Go to last post
  11. Read DDR to file using HPS2FPGA

    Started by ela05jdc, September 8th, 2017 10:12 AM
    arrow, hps, hps2fpga, soc, sockit
    • Replies: 1
    • Views: 662
    October 16th, 2017, 01:33 AM Go to last post
  12. Connect FFT IP core and QSYS

    Started by ezequiel, October 10th, 2017 04:53 AM
    • Replies: 0
    • Views: 394
    October 10th, 2017, 04:53 AM Go to last post
  13. Disable FPU on Arria10 SoC FPGA

    Started by karthik.k, August 29th, 2017 12:17 AM
    • Replies: 6
    • Views: 1,512
    October 8th, 2017, 03:15 AM Go to last post
  14. make_sdimage.py creates invalid ext3 partition

    Started by billr, December 13th, 2016 09:20 PM
    • Replies: 1
    • Views: 1,090
    September 27th, 2017, 03:12 AM Go to last post
  15. Question Linux Console with framebuffer on DE10-nano SOC

    Started by yazbek, September 25th, 2017 12:39 AM
    • Replies: 0
    • Views: 488
    September 25th, 2017, 12:39 AM Go to last post
  16. DE1-SoC Interfacing with ADXL345 3 Axis Accelerometer [I2C]

    Started by XXRyanXXL, September 14th, 2017 09:46 AM
    • Replies: 1
    • Views: 629
    September 23rd, 2017, 09:13 AM Go to last post
  17. Unhappy YoctoPlugin SoCKit Altera Cyclone 5

    Started by geogrebust, September 22nd, 2016 06:46 AM
    • Replies: 1
    • Views: 1,360
    September 15th, 2017, 07:47 AM Go to last post
    • Replies: 0
    • Views: 550
    September 7th, 2017, 01:24 PM Go to last post
    • Replies: 0
    • Views: 522
    August 31st, 2017, 11:20 PM Go to last post
  18. Uart Baud Rate Drop

    Started by stefanri, August 17th, 2017 08:09 AM
    • Replies: 4
    • Views: 825
    August 22nd, 2017, 10:32 AM Go to last post
  19. SPI communication

    Started by seongjinkim, August 22nd, 2017 04:42 AM
    • Replies: 0
    • Views: 509
    August 22nd, 2017, 04:42 AM Go to last post
  20. Altera avalon I2C

    Started by kgandhi0408, August 18th, 2017 04:39 AM
    • Replies: 1
    • Views: 694
    August 18th, 2017, 10:03 PM Go to last post
  21. Fixed-link Feature

    Started by MartinFeng_Cytech, August 17th, 2017 01:23 AM
    • Replies: 0
    • Views: 532
    August 17th, 2017, 01:23 AM Go to last post
  22. Questions about SOC FPGA Preloader and device tree

    Started by OmranAbazid, May 23rd, 2017 03:40 PM
    • Replies: 9
    • Views: 2,719
    August 1st, 2017, 01:28 AM Go to last post
  23. Qsys Custom Peripheral Memory Mapping

    Started by FlipFlop, July 26th, 2017 09:53 PM
    custom peripheral, interrupt, nios, qsys
    • Replies: 2
    • Views: 881
    July 28th, 2017, 01:59 PM Go to last post

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