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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 533
    • Posts: 2,021
  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 226
    • Posts: 588
  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    • Threads: 16
    • Posts: 44

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  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    • Threads: 80
    • Posts: 271

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  5. A place to discuss booting SoC devices and the bootloader that makes this happen

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    Forum Statistics:

    • Threads: 92
    • Posts: 352
  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 12:29 PM
    • Replies: 0
    • Views: 10,931
    January 27th, 2015, 12:29 PM Go to last post
  1. Arria 10 EPCQL Controller

    Started by limshutian, Today 04:04 PM
    • Replies: 0
    • Views: 27
    Today, 04:04 PM Go to last post
  2. Exclamation ARM DS-5 and DE10-Nano

    Started by aignacio, February 7th, 2018 10:52 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 495
    Yesterday, 07:26 PM Go to last post
  3. Niosll vga output

    Started by FPGA_guru011, February 18th, 2018 11:21 PM
    • Replies: 1
    • Views: 80
    Yesterday, 06:04 PM Go to last post
  4. creating custom multiple registers

    Started by smruthi, December 12th, 2017 05:00 AM
    custom component, nios2
    • Replies: 6
    • Views: 790
    Yesterday, 05:20 AM Go to last post
  5. Some questions about Arria 10 PCI Express HIP and topologies

    Started by Cotton, February 13th, 2018 07:04 AM
    altera, arria, hip, intel, pci
    • Replies: 0
    • Views: 140
    February 13th, 2018, 07:04 AM Go to last post
  6. de10 nano ethernet phy clock loanio

    Started by letrend, January 12th, 2018 05:28 PM
    • Replies: 2
    • Views: 375
    February 13th, 2018, 04:57 AM Go to last post
  7. Touch LCD for DE10 nano and compare with BeagleBoard

    Started by egywell, January 29th, 2018 07:30 AM
    • Replies: 2
    • Views: 250
    February 12th, 2018, 11:21 PM Go to last post
  8. [Arria 10] Implementation of a PCI Express "Host" solution

    Started by remhi.ch, February 8th, 2018 06:25 AM
    arria, express, host, pci, rootcomplex
    • Replies: 0
    • Views: 493
    February 8th, 2018, 06:25 AM Go to last post
  9. Cyclone V SoC using LTC2978 sensor for voltage monitoring

    Started by nekuss1, February 5th, 2018 07:58 AM
    • Replies: 3
    • Views: 275
    February 6th, 2018, 06:52 AM Go to last post
  10. EM2130L Regulator with external Sync clock

    Started by bhavishya aj, February 5th, 2018 05:50 AM
    • Replies: 1
    • Views: 198
    February 5th, 2018, 09:09 PM Go to last post
  11. NIOS GPIO and Metastability question

    Started by berretto77, February 5th, 2018 01:39 AM
    nios gpio metastability
    • Replies: 0
    • Views: 81
    February 5th, 2018, 01:39 AM Go to last post
  12. Cyclone V SoC doubt

    Started by joel.sanchez, January 27th, 2018 03:03 AM
    arm, cyclone v, fpga, soc
    • Replies: 4
    • Views: 443
    January 29th, 2018, 12:46 PM Go to last post
  13. Cyclone V SoC - Time execution function - Cycle count

    Started by Remy ASTIER, January 21st, 2015 12:58 AM
    • Replies: 4
    • Views: 6,667
    January 29th, 2018, 08:58 AM Go to last post
    • Replies: 2
    • Views: 444
    January 17th, 2018, 02:45 PM Go to last post
  14. Question HPS SPI Master with more than 4 Slave Selects

    Started by Designer777, January 12th, 2018 06:42 AM
    arria 10, slave select, soc, spi, spi master controller
    • Replies: 1
    • Views: 388
    January 13th, 2018, 08:20 PM Go to last post
    • Replies: 7
    • Views: 822
    January 8th, 2018, 10:44 AM Go to last post
  15. Memory map error in software program

    Started by karthik.k, January 7th, 2018 09:31 PM
    • Replies: 0
    • Views: 521
    January 7th, 2018, 09:31 PM Go to last post
  16. Set initial value at beginning

    Started by Doug314, December 30th, 2017 08:25 AM
    • Replies: 4
    • Views: 740
    January 1st, 2018, 07:15 AM Go to last post
  17. 5CSEBA2 Cyclone V SOC HPS-DDR3 w/ECC

    Started by vanlandingham10, December 18th, 2017 01:25 PM
    5cseba2, cyclone v, ddr3, ecc
    • Replies: 0
    • Views: 469
    December 18th, 2017, 01:25 PM Go to last post
    • Replies: 2
    • Views: 694
    December 14th, 2017, 02:20 AM Go to last post
  18. Address Span Extender

    Started by MUTHUVENKATESH, November 30th, 2017 02:08 AM
    • Replies: 1
    • Views: 827
    December 10th, 2017, 03:42 AM Go to last post
  19. UART encoding issues

    Started by koded, December 8th, 2017 09:16 AM
    • Replies: 1
    • Views: 558
    December 9th, 2017, 02:54 AM Go to last post
  20. Fpga -qt

    Started by KANZALI, December 3rd, 2017 04:22 AM
    • Replies: 1
    • Views: 613
    December 3rd, 2017, 07:23 PM Go to last post
    • Replies: 1
    • Views: 738
    December 1st, 2017, 11:46 PM Go to last post
  21. Tristate bridge controller parameters

    Started by berretto77, November 30th, 2017 05:54 AM
    • Replies: 0
    • Views: 594
    November 30th, 2017, 05:54 AM Go to last post
  22. Verify functionality of design in arria 10 SoC

    Started by karthik.k, November 29th, 2017 01:50 AM
    • Replies: 0
    • Views: 1,033
    November 29th, 2017, 01:50 AM Go to last post
  23. Cyclone V SOC F2S Arbitration

    Started by shaiko, November 24th, 2017 04:14 AM
    • Replies: 0
    • Views: 659
    November 24th, 2017, 04:14 AM Go to last post
  24. Cyclone V HPS Memory

    Started by koded, November 18th, 2017 02:32 PM
    • Replies: 2
    • Views: 796
    November 20th, 2017, 11:08 PM Go to last post
    • Replies: 4
    • Views: 2,429
    November 18th, 2017, 09:08 PM Go to last post
  25. Cyclone V, sharing memory between FPGA and HPS

    Started by skliarovartem, November 13th, 2017 04:21 AM
    • Replies: 3
    • Views: 804
    November 13th, 2017, 10:06 AM Go to last post

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