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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 03:36 PM
    • Replies: 0
    • Views: 12,830
    October 14th, 2014, 03:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 02:37 PM
    • Replies: 0
    • Views: 31,985
    July 19th, 2013, 02:37 PM Go to last post
  1. Cyclone V SoC Preloader will not run bare metal app

    Started by jwdonal, September 5th, 2017 12:52 AM
    • Replies: 3
    • Views: 481
    September 6th, 2017, 06:20 PM Go to last post
  2. How to let FPGA get access to HPS pins

    Started by davidc85, March 27th, 2014 04:44 AM
    2 Pages
    1 2
    • Replies: 13
    • Views: 30,326
    September 3rd, 2017, 11:44 PM Go to last post
  3. HPS - FPGA used inside block diagram file.

    Started by ruben.vinuela, March 18th, 2015 09:52 AM
    • Replies: 3
    • Views: 3,137
    September 2nd, 2017, 07:52 AM Go to last post
  4. DE1-SOC power button non-functioning in AS/EPCS mode

    Started by Micks, August 31st, 2017 05:24 AM
    active serial, de1-soc, epcs, power button
    • Replies: 0
    • Views: 274
    August 31st, 2017, 05:24 AM Go to last post
  5. preloader not loading u-boot image

    Started by merciyy, August 17th, 2017 05:43 PM
    baremetal, preloader, sdcard boot
    • Replies: 6
    • Views: 853
    August 22nd, 2017, 10:04 AM Go to last post
  6. Post D5M not working with DE1-SoC

    Started by mderryberry, September 16th, 2014 01:30 PM
    d5m, de1-soc, image processing, vga
    • Replies: 5
    • Views: 14,197
    August 16th, 2017, 08:24 PM Go to last post
  7. AXI Problem when simulating Cyclone 5 SOC in Cadence NCSim

    Started by andrewrp, August 11th, 2017 08:16 AM
    • Replies: 0
    • Views: 320
    August 11th, 2017, 08:16 AM Go to last post
  8. How to set up shared on-chip memory

    Started by sonicsmooth, August 3rd, 2017 09:33 AM
    • Replies: 0
    • Views: 397
    August 3rd, 2017, 09:33 AM Go to last post
  9. Custom Spi Interface controlled by HPS in Arria 10

    Started by Marco Lobba, July 25th, 2017 04:15 AM
    • Replies: 1
    • Views: 471
    August 1st, 2017, 12:46 AM Go to last post
  10. Shared HPS pins pin planning on Arria 10

    Started by Marco Lobba, July 27th, 2017 07:32 AM
    • Replies: 1
    • Views: 419
    July 27th, 2017, 07:31 PM Go to last post
  11. How to work with FPGA-to-HPS bridge

    Started by Sergey, July 24th, 2017 06:06 AM
    • Replies: 0
    • Views: 403
    July 24th, 2017, 06:06 AM Go to last post
  12. FPGA to HPS (AXI Slave) address range issue

    Started by aurash, July 19th, 2017 09:04 AM
    hps
    • Replies: 1
    • Views: 518
    July 19th, 2017, 05:03 PM Go to last post
  13. Seeking HSMC-Transceiver setup assistance for C5G Eval Board

    Started by Scei, July 17th, 2017 08:58 AM
    • Replies: 1
    • Views: 466
    July 19th, 2017, 09:45 AM Go to last post
  14. DE1-SoC problem with tree please HELP!!

    Started by juatafe, July 4th, 2017 01:32 AM
    • Replies: 5
    • Views: 1,176
    July 5th, 2017, 11:51 PM Go to last post
  15. Arria V SOC clock sources

    Started by arria_v_soc_user, August 12th, 2014 03:55 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 16,609
    July 5th, 2017, 10:14 AM Go to last post
  16. MAC Address changes on reboot

    Started by DaveHorne, January 21st, 2014 07:24 AM
    • Replies: 7
    • Views: 22,872
    June 19th, 2017, 11:23 AM Go to last post
  17. Question Routing of I2C0 pins on SoC

    Started by Luki B, December 22nd, 2016 12:10 AM
    i2c, qsys, routing, soc
    • Replies: 3
    • Views: 2,069
    June 14th, 2017, 12:39 AM Go to last post
  18. DE0-nano: JTAG breaks when loading from EPCS

    Started by ISE_benny, June 7th, 2017 06:54 AM
    • Replies: 0
    • Views: 578
    June 7th, 2017, 06:54 AM Go to last post
  19. Cyclone V, HPS SPI routing to FPGA pins

    Started by Captain-Chaos, January 13th, 2017 01:35 AM
    • Replies: 3
    • Views: 2,423
    May 29th, 2017, 01:36 AM Go to last post
  20. Configuring IO on Cyclone V after boot

    Started by larso, May 10th, 2017 12:55 PM
    • Replies: 0
    • Views: 959
    May 10th, 2017, 12:55 PM Go to last post
  21. High bandwidth data transfer between hps and fpga

    Started by mojcmos, September 8th, 2016 03:50 AM
    3 Pages
    1 2 3
    • Replies: 20
    • Views: 4,962
    April 25th, 2017, 11:38 PM Go to last post
  22. Arria 10 - Ubuntu - make error for Uboot

    Started by lemonoje, April 25th, 2017 11:58 AM
    • Replies: 0
    • Views: 1,016
    April 25th, 2017, 11:58 AM Go to last post
  23. HPS Configuration in QSys: Why is hps_io exported?

    Started by DrTobbe, April 13th, 2017 06:29 AM
    hps, pin muxing, qsys
    • Replies: 3
    • Views: 1,666
    April 25th, 2017, 08:30 AM Go to last post
  24. FPGA-to-HPS SDRAM Interface Problem

    Started by helekjo, April 20th, 2017 04:31 AM
    • Replies: 1
    • Views: 1,234
    April 24th, 2017, 02:04 AM Go to last post
  25. Cyclone V SoC - Shared Memory Controller

    Started by Taz1984, July 15th, 2013 10:20 PM
    6 Pages
    1 2 3 ... 6
    • Replies: 51
    • Views: 59,072
    April 15th, 2017, 01:25 AM Go to last post
  26. GPIO access in Deo nano cyclone

    Started by sravich81, April 14th, 2017 12:39 AM
    • Replies: 0
    • Views: 1,062
    April 14th, 2017, 12:39 AM Go to last post
  27. Connecting HPS GPIOs to top level pins

    Started by QsXiang, April 7th, 2017 11:22 AM
    • Replies: 0
    • Views: 1,085
    April 7th, 2017, 11:22 AM Go to last post
  28. fpga for solar inverter and power electronics applications

    Started by engma, April 2nd, 2017 05:57 AM
    • Replies: 0
    • Views: 1,062
    April 2nd, 2017, 05:57 AM Go to last post
  29. Arria 10 Soc DevKit Golden Top will not build

    Started by dnovick238, March 30th, 2017 09:47 AM
    arria 10 soc, build fail, dev kit, golden top
    • Replies: 1
    • Views: 1,503
    March 31st, 2017, 06:07 AM Go to last post
  30. Accessing HPS-SDRAM from the FPGA

    Started by horacioEsta, March 21st, 2017 12:50 PM
    • Replies: 0
    • Views: 1,173
    March 21st, 2017, 12:50 PM Go to last post

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