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Thread: Avalon MM slave custom component: register reading/writing issue

  1. #11
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    Default Re: Avalon MM slave custom component: register reading/writing issue

    Hi, Thanks for the above, very helpful.

    But I am still having trouble outputting data from a bidirectional PIO.
    I am working with a DE0-Nano-SoC, in C in Linux, and have created 2 output only PIOs,
    which work fine.

    I also have a bidirectional data PIO that can read readonly registers in my firmware,
    but if I write data to read/write registers in my firmware, and then read it back, it is always 0.
    Tracing with SignalTap shows no data being output from the PIO on write.

    Below is the crucial code, I am hoping someone can see where I am going wrong.
    Is it the address calculation for the Data Direction register ?

    This is for the Data register (which works for the output only PIOs) :
    h2p_lw_pio_d_addr=virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_D_BASE ) & ( unsigned long)( HW_REGS_MASK ) );

    Is this right for the Data Direction register ?
    h2p_lw_pio_d_dirn = virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_D_BASE + 1 ) & ( unsigned long)( HW_REGS_MASK ) );



    I am setting this as :
    Write :
    Set Data (8 bit) :
    Data = strtol(argv[4], &strptr, 10); // Data to write
    *(uint32_t *)h2p_lw_pio_d_addr = Data;
    Output it :
    *(uint32_t *)h2p_lw_pio_d_dirn = 0xff ; // All PIO Data bits set to output (write)


    Set Input :
    *(uint32_t *)h2p_lw_pio_d_dirn = 0x00 ; // All PIO Data bits set to input (read)
    Read Data :
    SkelData_read = *(uint32_t *)h2p_lw_pio_d_addr;

    Thanks,
    Beau Webber
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    Last edited by BeauWebber; January 13th, 2018 at 03:40 PM. Reason: typo

  2. #12
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    Default Re: Avalon MM slave custom component: register reading/writing issue

    Try it like this:

    h2p_lw_pio_d_dirn = virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_D_BASE + 4 ) & ( unsigned long)( HW_REGS_MASK ) );

    The gpio_swporta_ddr (data direction) register offset is 0x4, not 0x1, according to cv_5_hps_trm.pdf manual.

  3. #13
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    Default Re: Avalon MM slave custom component: register reading/writing issue

    Quote Originally Posted by austin944 View Post
    Try it like this:

    h2p_lw_pio_d_dirn = virtual_base + ( ( unsigned long )( ALT_LWFPGASLVS_OFST + PIO_D_BASE + 4 ) & ( unsigned long)( HW_REGS_MASK ) );

    The gpio_swporta_ddr (data direction) register offset is 0x4, not 0x1, according to cv_5_hps_trm.pdf manual.
    Yes indeed you are quite correct, that works fine, thank you very much.
    I can now read and write the registers in my firmware.
    I understand the 4 vs 1 is a matter of byte vs word addressing.
    I now have 4 of the "instruments" from my Cyclone II firmware installed in the DE0-Nano-SoC fabric, and under test.
    Sorry to be a pain, but can you give me a link to the cv_5_hps_trm.pdf manual ? I have searched the Altera site and not yet found it.














    .

  4. #14
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    Default Re: Avalon MM slave custom component: register reading/writing issue

    Is it a Cyclone IV device on the DE0-Nano board?

    I used the Cyclone V manual since that's what I have available in my board (DE10-Nano).
    The Cyclone V HPS Technical Reference manual is here:
    https://www.altera.com/documentation...143707420.html
    Page 22-4, GPIO Module Address Map.

    Try here to search for the corresponding Cyclone IV manual:
    https://www.altera.com/products/fpga...v/support.html
    Last edited by austin944; January 22nd, 2018 at 01:14 PM.

  5. #15
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    Default Re: Avalon MM slave custom component: register reading/writing issue

    Oh thanks indeed.
    I am using the DE0-Nano-SoC board, which has a Cyclone V :

    Programmable Logic IC Development Tools Cyclone V SE 5CSEMA4U23C6N + 800MHz Dual-core ARM Cortex-A9 processor
    http://www.terasic.com.tw/cgi-bin/pa...yNo=205&No=941
    https://www.mouser.co.uk/new/terasic...atlas-soc-kit/

    Except for the point that you have helped me over I have found it a very easy and flexible system to work with.
    The two rows of GPIO connectors map well to similar double rows of connectors on my Cyclone II modules, and is allowing me to port hardware as well as the firmware.
    Last edited by BeauWebber; January 22nd, 2018 at 01:36 PM. Reason: better link

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