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Thread: DMA read timeout while using PL330?

  1. #1
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    Default DMA read timeout while using PL330?

    Hi

    we are using the HPS-DMAC (PL330) on a De0-Nano-SoC board to write and read data from the FPGA through a kernel module using the dmaengine API. Writing works fine (albeit pretty slow), but everytime we try to read data from the FPGA, a timeout occurs. The kernel module ist largely based on the fpga-dma driver provided by altera. I can see that the read transfer is arriving at my module in the FPGA (which is just a loopback FIFO), but for some reason the DMA callback function is never called and so a timeout occurs.

    When I remove the timeout from the kernel module, the first transfer still arrives in the FPGA and reads some data. All following read-request dont reach the FPGA until I call a write to the FPGA. When executing the write, the read callback is called and the next read begins. This is very weird to me, I don't understand how the write call can call both the read and write callbacks.

    My question is: what determines the end of a read access for the DMAC? Do I have to implement some additional signal in the avalon bus?

    I hope someone can give us a hint! If you need any more information or code samples, please let me know!

    Thanks in advance!
    Last edited by Brillow; May 12th, 2016 at 08:55 AM. Reason: Calrified behavior without timeout

  2. #2
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    Default Re: DMA read timeout while using PL330?

    Did you ever get anywhere with this problem? I am having a similar problem. Using the fpga-dma example I want to read data from a fifo on the lwhpsslave.
    Its a custom board, but a cyclone v soc just like the de0-nano-soc. I am running 4.2 kernel. Seems to load the driver ok. But I get no errors and no data transfer.
    Like you its just pending. Programmed Io works fine.

    [ 0.300924] dma-pl330 ffe01000.pdma: Loaded driver for PL330 DMAC-341330
    [ 0.300943] dma-pl330 ffe01000.pdma: DBUFF-512x8bytes Num_Chans-8 Num_Peri-32 Num_Events-8

    Thanks,

    Jeff

  3. #3
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    Default Re: DMA read timeout while using PL330?

    Hi all,

    I am trying to write a module to do transfers using pl330 DMA controller from processor to FPGA and from FPGA to processor using Cyclone V SoC and Angstrom Linux 3.10. So far what I have found are examples for Zynq using DMA engine API and directly PL330 API. They dont compile because macros, structs, etc. are different. All the examples I have found for Altera use DMA-engine for a DMA controller in the FPGA. Could someone answer some of these questions?:

    -Where can I find the so called fpga-dma driver provided by altera that other people is refering to?
    -Which OS are you using? Is it OK using Angstrom? Do I have to do something special during OS compilation to get DMA drivers included? Teorethically after 3.8 kernel DMA engine is available.
    -I could not do the binding to the device tree entry for the pl330. I do the platform driver registering process but probe function is never called. I can see the value of compatible string in proc/device-tree/sopc@0/dma@0xffe01000 is: "arm,pl330-14.1arm,pl330,arm,primecell"
    I tried thye binding with "arm,pl330-14.1", "arm,pl330", "arm,primecell" and "arm,pl330-14.1arm,pl330,arm,primecell". Nothing is working. Probe function does not pop out.

    I would appreciate any help

  4. #4
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    Default Re: DMA read timeout while using PL330?

    May be we could help.
    We have a PL330 DMA driver for the Cyclone V / Arria 5 / Arria 10 shipped with our RTOS.
    You can get the free standalone version of our BSP (it includes the DMA driver).
    The standalone package is completely independent of RTOS, library, or anything else.
    You can request it at: code-time.com
    It's somewhere in the "board support" section

    There are hooks to dump the debug registers of the PL330.
    And that's quite informative to understand what is going on.
    ... may be I should say: what's not going on.

    Regards

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